I'm trying to implement a spread spectrum clock generator using a digitally controlled delay line in Verilog.
The basic idea is that I'm trying to modulate the period of my clock signal using some and_gates that each have a delay value assigned to them. The delay network just delays the signal, but it does not change the period of the clock signal.
Is this concept even possible(modifying the period of the clock, by passing it through some and_gates) using Verilog?
To delay a pulse train, one easy method is to send it through an RC integrator. This results in a ramping (or quasi-triangular) waveform. Restore DC pulses by following up with a logic gate.
Shift the delay forward or backward by adjusting values.
But I'm trying to change the Period/frequency of the clock signal, not just to delay it. I believe it can be delayed just by passing it through some buffers.
For xilinx FPGA's you would use the iodelay elements. They have control systems to reduce the impact of process/voltage/temperature changes. Altera/Intel likely have something similar.
@bubu_not_taken, For xilinx, look at the iodelay system. You don't get the 1:1 semantics you want, but you can adjust delays precisely and dynamically.
also, your question is not well formed. "modulate the period" and "does not change the period" combined are impossible -- modulate implies some change.