Spikes in pipelined ADC stage

[moisiad]

Hi all

I have completed the design of the basic S/H stage of a 1.5Bit pipelined ADC converter (VDD=1V, Fclk=40MHz, Input signal swing 0.25V-0.75V).
After simulations i have noticed that when the input is quantized, except the steps in the output i get spikes during the transitions of the clock which can be as large as 50-60mV.
Is this normal? Is this due to the switches-capacitor network or due to the OPAPM (folded cascoded)?

Thanks

 

[Btrend]

it is from
1. clock feedthrough
2. charge injection

 

[andy2000a]

S/H switch use "dummy Mos" can really reduce charge injection , I ever use 1/2 size dummy Mos siwtch , but simulation sitll have charge injection

maybe small switch W/L reduce , and reduce parastic Cap for reduce clock feedthrough

 

[tuza2000]

you can try the cmos switch.
there no ways to eliminate the charge injection.
regards

 

[sunking]

You can use "bottom sampling" method to eliminate the charge injection.

 

[moisiad]

Thank you all for your help.

I have adopted most of your suggestions (CMOS switches, bottom plate sampling, dummy transistors) but unfortunattely there was no significant improvenment.

However i am wondering if that spikes will affect the overall system performance or not? I suspect that if (generally speaking for a SH circuit) the signals are stable (and clear from spikes) during the hold phase then any spikes generated during the transition from the sample to the hold phase are out of concern. Am i wrong?

Thanks for your interest

 

[sunking]

You can run a .tr to analysis.
input a sine wave and dump the output data for a fft analysis.
yes, in fact, most of the spikes will not affect the system.