[SOLVED] SPI slave module question

[hsnhsyn1]

Hi, i'm working for a SPI slave module on fpga with verilog. I have not used SPI before, so i don't know it well. I just read and looked some examples about it.

http://www.fpga4fun.com/SPI2.html

-> on this website it's very simple i think. but there are some points i couldn't understand.

in this part, they used a shift register for SCK. i know that SCK is produced by the master device, but the thing i don't understand is why SCK needs to be a register, and is not used like a clock signal?

// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr;  always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01);  // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10);  // and falling edges

and the other thing is, what do they mean with "first byte sent in a message is the message count"? why is it different from the data receiving counter?

reg [7:0] byte_data_sent;

reg [7:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+8'h1;  // count the messages

always @(posedge clk)
if(SSEL_active)
begin
  if(SSEL_startmessage)
    byte_data_sent <= cnt;  // first byte sent in a message is the message count
  else
  if(SCK_fallingedge)
  begin
    if(bitcnt==3'b000)
      byte_data_sent <= 8'h00;  // after that, we send 0s
    else
      byte_data_sent <= {byte_data_sent[6:0], 1'b0};
  end
end

assign MISO = byte_data_sent[7];  // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive

endmodule

if anyone can help, i would be grateful.

 

[FvM]

There are essentially two ways to operate an SPI slave:
- clock the receiving logic by SCK, transfer the data wordwise to and from the system clock domain using domain crossing techniques, e.g. handshake.
- clock the receiving logic by the system clock, synchronize the serial SPI signals to the system clock domain

The posted code uses the second approach, presuming a SPI clock frequency that's sufficiently low compared to the system clock.

first byte sent in a message is the message count

An application specific point that hasn't to do with SPI in general.

 

[hsnhsyn1]

okay, so i can count the sent data as the received one?

what about this slave select part? i couldn't quite understand the purpose of SSEL_startmessage and SSEL_endmessage. i mean when the SSEL is active, isn't it always zero after it's activated?

reg [2:0] SSELr;  always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1];  // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10);  // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01);  // message stops at rising edge

and in this part, why is it sending zeros?

if(SCK_fallingedge)
  begin
    if(bitcnt==3'b000)
      byte_data_sent <= 8'h00;  // after that, we send 0s
    else
      byte_data_sent <= {byte_data_sent[6:0], 1'b0};
  end

 

[FvM]

The example code isn't sending real data, only the said message count. Thus it's zeroing transmit data after the first byte.

As you recognized correctly, the startmessage and endmessage triggers are set for one clock cycle.

Instead of trying to understand the purpose of a very specific SPI slave example without much explanations, you should better design a SPI module according to your requirements.

 

[hsnhsyn1]

I'll try that. thank you very much.