reg [7:0] byte_data_sent;
reg [7:0] cnt;
always @(posedge clk) if(SSEL_startmessage) cnt<=cnt+8'h1; // count the messages
always @(posedge clk)
if(SSEL_active)
begin
if(SSEL_startmessage)
byte_data_sent <= cnt; // first byte sent in a message is the message count
else
if(SCK_fallingedge)
begin
if(bitcnt==3'b000)
byte_data_sent <= 8'h00; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
end
assign MISO = byte_data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
endmodule