You didn't connect something up in the testbench, or you didn't follow the correct protocol, or you didn't follow the slaves address map, or something else is wrong.
One observation is you're code is badly written, it's written as if Verilog is a procedural language like C. This code doesn't describe hardware it's a program (with an assignment statement assign i=i+1; inside a always block, SYNTAX ERROR). You should read a Verilog book or at least a tutorial on how to write Verilog code for synthesis as it's obvious that you don't know the language well enough to write code.