SPI interface Vivado/SDK

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i.e. As I understood it - If you are using only 1 SPI channel then this core from Xilinx can also be used as a slave device (1 SPI master can be connected to it). If you want to use more channels, then this core will only act as master device and all connected SPI devices will be slaves.

Quad SPI is a modification to SPI that increases data bandwidth by making the data bus 4-bits instead of 1-bit, quadrupling the transfer rate. It does not increase the number of slave channels supported, that still is done using address decode and mux/demux logic. The only reason Xilinx didn't support QSPI as a slave as the protocol is primarily used for QSPI flash devices for programing FPGAs or as data storage devices. Therefore there isn't much of a need or requests for a QSPI slave core to support FPGA control (as you wouldn't want to use an FPGA as a flash memory device.)

Hi,
I would like to know theoritically what will be difference when working as slave compared to working as master?

Slave - only accepts transfers from a master can not initiate a transfer, responds the read and write requests.
Master - initiates all transfers, both reads and writes are initiated by the master device.

Can I say I even don't need to configure access to my program as SPI slave to be controlled from external SPI Master rather just provide access to the register(GPIO pin) to external master?

Not sure what you are tying to convey here.

To support UART-like SPI you need to either use both a SPI master and SPI slave on both sides of the interface so either end can start a transfer, or you need to send information back on the MISO line when you send data on the MOSI line, this will only be useful if you need a response from the slave when you perform a write. Otherwise you may have to poll the slave for some return status. (UARTs just send stuff back whenever they feel like)

 

[beginner_EDA]

As indicated by dpaul in #18, I used IObuff to connect AXI Quad SPI having trisate pins to gpio pin. But after synthesis, it seems only t pin is connected with iobuff but not i and o.
(see attachment).

This is how I instantiate iobuff (only one shown here):

mosi_IOBUF_inst : IOBUF
port map (
O => spi_rtl_io0_o_int , -- Buffer output
IO => gpio0, -- Buffer inout port (connect directly to top-level port)
I => spi_rtl_io0_i_int , -- Buffer input
T => spi_rtl_io0_t_int -- 3-state enable input, high=input, low=output
);

and these internal signals spi_rtl_io0_o_int, spi_rtl_io0_i_int and spi_rtl_io0_t_int I connected to SPI corresponding tristate pins as:

spi_i : spi
port map (
     sys_diff_clock_clk_p                     => sys_clk_p,    
     sys_diff_clock_clk_n                     => sys_clk_n,    
     reset   =>  reset,
     spi_rtl_io0_i => spi_rtl_io0_i_int,
     spi_rtl_io0_o =>  spi_rtl_io0_o_int,
     spi_rtl_io0_t =>  spi_rtl_io0_t_int,
     spi_rtl_io1_i =>  spi_rtl_io1_i_int,
     spi_rtl_io1_o =>  spi_rtl_io1_o_int,
     spi_rtl_io1_t =>  spi_rtl_io1_t_int,
     spi_rtl_sck_i =>  spi_rtl_sck_i_int,
     spi_rtl_sck_o =>  spi_rtl_sck_o_int,
     spi_rtl_sck_t =>  spi_rtl_sck_t_int,
     spi_rtl_spisel => '0',--spi_rtl_spisel_int,
     spi_rtl_ss_i  => spi_rtl_ss_i_int,
     spi_rtl_ss_o  => spi_rtl_ss_o_int,
     spi_rtl_ss_t  => spi_rtl_ss_t_int
  );

What is wrong here. i didn't receive any input from gpio? how to connect tristate pin of spi to gpio?

 

[dpaul]

Port map looks ok.

But I am worried as to how the SPI core top-level ports are. It is very different from what you posted in #13.

 

[beginner_EDA]

Hi dpaul,
the c file you mentioned in #10 is sufficient for spi as a slave?
After exporting hardware in SDK, 2 .h file is generated as spi driver (see attachment in txt form).
There also following function in xspi_l.h file to read and write:

#define XSpi_ReadReg(BaseAddress, RegOffset) \
XSpi_In32((BaseAddress) + (RegOffset))

#define XSpi_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XSpi_Out32((BaseAddress) + (RegOffset), (RegisterValue))

I am wondering how to read/write spi as slave from external master? Do I need some configure/interrupt stufff etc?

 

[dpaul]

The eg C code I presented earlier was just a generic sample code to show how to read or write an AXI address using the uBlaze.
You have to modify it as per use case. You have to know the AXI address range (assuming that the uB is connected to the Xilinx core via AXI bus) on which the SPI core sits. You should also keep address offsets in mind if any.

A very simple random e.g. - if an SPI register address is 0000_001a and if the SPI core sits between the address range 0001_0000 and 000e_ffff, then to read from this SPI register, you have tell the uBlaze to read from register address 0001_001a.

If you have a .h file generated for the SPI then things should be much more simpler.

I am loaded with work at office so I don't have time to look into the specifics of the files you have posted. So I can only provide generic guidance at this point in time. Someone who has worked with this Xilinx SPI core can give you specific inputs.

As a first exercise just try to read the SPI status register and then work your way up to more complex operations.

 

[beginner_EDA]

Hi,
this is how I proceeded after reading its driver and internet source:

#include <stdio.h>
#include <stdlib.h>
#include "xparameters.h"
#include "xil_cache.h"
#include "xspi.h"
#include "xspi_l.h"
#include "xbasic_types.h"

#define SPI_DEVICE_ID		XPAR_SPI_0_DEVICE_ID
#define SPI_SELECT 0x01
#define LED_CHANNEL 1

int main()
{
	static XSpi Spi;

	int Status;

	u8 ReadBuffer;

	XSpi_Config *ConfigPtr;	/* Pointer to Configuration data */

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	xil_printf("---Entering main---\n\r");

	 // Initialize the SPI driver so that it is  ready to use.
	ConfigPtr = XSpi_LookupConfig(SPI_DEVICE_ID);
	if (ConfigPtr == NULL) {
		return XST_DEVICE_NOT_FOUND;
	}

	Status = XSpi_CfgInitialize(&Spi, ConfigPtr,ConfigPtr->BaseAddress);
	if (Status == XST_SUCCESS)
   	{
    		xil_printf("Spi Initialize success!\n\r");
   	}
   	else
   	{
    		xil_printf("Spi Initialize failed!\n\r");
   	}

	 // Set the SPI device as a master and in manual slave select mode such
	 // that the slave select signal does not toggle for every byte of a
	 // transfer, this must be done before the slave select is set
	Status = XSpi_SetOptions(&Spi, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION);
	if (Status != XST_SUCCESS)
	{
		return XST_FAILURE;
	}

	// Select the slave on the SPI bus so that it can be
	// read and written using the SPI bus
	XSpi_GetSlaveSelect(&Spi);

	Status = XSpi_SetSlaveSelect(&Spi, SPI_SELECT);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	// Start the SPI driver so that interrupts and the device are enabled
	Status = XSpi_Start(&Spi);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	//disable global interrupts since we will use a polled approach
	XSpi_IntrGlobalDisable(&Spi);


/*
*	XSpi_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
*	The caller wishes to only receive and does not care about sending
*	data.  In this case, the caller must still provide a send buffer, but
*	it can be the same as the receive buffer if the caller does not care
*	what it sends. The device must send N bytes of data if it wishes to
*	receive N bytes of data.
*/
	Status = XSpi_Transfer(&Spi, ReadBuffer, ReadBuffer, 1);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	xil_printf("ReadBuffer = 0x%x\r\n", ReadBuffer);

	xil_printf("---Exiting main---\n\r");

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}

just wanted to know to read spi bus, should I use

XSpi_Transfer(&Spi, ReadBuffer, ReadBuffer, 1);

or

XSpi_ReadReg(&Spi.BaseAddr,0x70)