Have you read PG153, specifically pages 19 & 22? The signals are describe for both of these.Hi,
I have added SPI interface to my existing Project having UART interface (see screenshot in red marks) but I am not sure about:
1. where I am suppose to connect another 2 unconnected pins(STARTUP_IO and ip2intc_irpt).
don't know about this, I would have to attempt to implement this design, which I don't have time to do. Though each of these signals are likely the tri-state controls for their corresponding pins of the _o pin. I other words you are probably supposed to be instantiating tri-state (OBUFT) primitives for these outputs and these signals drive the tri-state control.2. following critical warning during bitsream generation:
[Netlist 29-160] Cannot set property 'BOARD_PIN', because the property does not exist for objects of type 'pin'. ["c:/FPGA/Three_Channels/xapp1199/xapp1199_v1_2/kc705_smpte2022_56_rx/VoIP_RX_10G/VoIP_RX_10G.srcs/sources_1/bd/system_basic/ip/system_basic_axi_quad_spi_0_0/system_basic_axi_quad_spi_0_0_board.xdc":3]
and pointing to generated xdc files:
set_property BOARD_PIN {SPI_IO0_T} [get_ports io0_t]
set_property BOARD_PIN {SPI_IO1_T} [get_ports io1_t]
set_property BOARD_PIN {SPI_SS_T} [get_ports ss_t]
But there are no such pin available with the user guide of kc705 fpga board. That means do I need to map some GPIO pin and make some physical connection by self?
The one called spi_flash is the spi interface. I'm not sure why you have this question. Maybe you don't know that this IP can be used for controlling the SPI configuration flash or as a standard 4-wire SPI master. Perhaps you are not configuring the right version?3. which port should I instantiate for spi part in top level design as pin is not clear to me.
It's controlled via the AXI4-Lite interface and the base address can be found in the Address Editor tab.4. After exporting hardware in SDK, where should I control spi part also not clear.
Hi, I am looking for 4 wires(CLK, MISO, SIMO, SS) SPI to read the output and give the command to system(microblaze) from outside like UART Terminal and surely not SPI configuration flash.The one called spi_flash is the spi interface. I'm not sure why you have this question. Maybe you don't know that this IP can be used for controlling the SPI configuration flash or as a standard 4-wire SPI master. Perhaps you are not configuring the right version?
Study the SPI IP spec carefully, it would be written there how these pins can be connected (don't have time to read the spec and extract that info for you).1. where I am suppose to connect another 2 unconnected pins(STARTUP_IO and ip2intc_irpt).
On top of what ads-ee has said, I would like to add that the *_t signals looks like tri-state buffer control signals and they cannot be connected directly to an FPGA i/o port. Use an OBUFT as ads-ee has mentioned.But there are no such pin available with the user guide of kc705 fpga board. That means do I need to map some GPIO pin and make some physical connection by self?
I think you are using the correct IP.But there is only one IP which is available in vivado. Does it mean I am not using the right one?
Hi,Bigger question is why are you using the SIP IP and what do you want to do with it?
/**
* Fetch input from UART then callback voip_contrl_app to
* process the selection
*/
#include "xuartlite_l.h"
void get_voip_ctrl_app_input(void)
{
if (!XUartLite_IsReceiveEmpty(STDIN_BASEADDRESS)){
inchar = (u8)XUartLite_ReadReg(STDIN_BASEADDRESS, XUL_RX_FIFO_OFFSET);
xil_printf("%c\n\r",inchar);
voip_ctrl_app(inchar);
voip_ctrl_app(CARRIAGE_RETURN);
}
}
Have you read the chapter "Testing the Example Design on a KC705 Board" in the pg153-axi-quad-spi.pdf document? There seems to be some info there!1. There is no pins of SPI in kintex kc705, how I can instantiate to top level module and specially how I can connect to outside world like via SPI cable or something like that?
Keep it simple. Just read-from/write-to valid AXI addresses.2. After exporting hardware to SDK, the base address available in Address Editor tab but don't know in which function should I use this address.
#include <stdio.h>
#include "platform.h"
#define LOC3 (*(unsigned int *)0xf0000000) // This is the axi address
int main()
{
init_platform();
LOC3 = 0xcafeface; // Write data "cafeface" to LOC3
cleanup_platform();
return 0;
}
This is the xdc file generated after adding spi ip :Basically you can to connect the SPI ports to the kc705 ports as standard i/p or o/p ports. So you can use any set of GPIO ports available on the Kintex
Hi,You can either use behavioral RTL description or directly instantiate the Xilinx primitive OBUFT (3-state output buffer).
Download the doc ug471_7Series_SelectIO.pdf, search for OBUFT and read how it behaves.
ENTITY system_basic_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_basic_axi_quad_spi_0_0;
OBUFT #(
.IOSTANDARD("DEFAULT"),
) OBUFT_inst (
.O( io0_o ),
.I(XADC_GPIO_0),
.T( io0_t)
);
The SPI module you are trying to add won't support what you want to do. The SPI module is a MASTER ONLY module, a master on the AXI controls the slave interface of the Quad SPI to control a master SPI to communicate with an external slave SPI. You want to use this as a terminal to control the FPGA which won't work.Hi,
I have UART Terminal for my project to control the program like setting IP address, UDP port etc from terminal and also to see the output (printf function) of the program on the terminal.
Now I would like to replace this task of UART with SPI.
and it's not clear to me how to proceed?
Code VHDL - [expand] 1 io_pin_name <= internal_signal_o when internal_signal_t = '0' else 'Z';
Hi,The SPI module you are trying to add won't support what you want to do. The SPI module is a MASTER ONLY module, a master on the AXI controls the slave interface of the Quad SPI to control a master SPI to communicate with an external slave SPI. You want to use this as a terminal to control the FPGA which won't work.
You would need a USB (or something) to a SPI master widget along with a SPI SLAVE ONLY module in your FPGA to support what you want to do.
Hi,
I don't have USB or something like that at the moment. Could you please clarify me how much of UART work is practically possible via SPI? Can I atleast read and write the register of the program via SPI?
This means at least for this purpose how I am proceeding above is right?You can read write registers in your FPGA (the SPI slave) using a SPI master
If you connect an IO buffer b/w the quad_spi ports and an FPGA IO pin then you are good to go.This means at least for this purpose how I am proceeding above is right?
It is written in the spec.I am supposed to use SPI as a slave and configured as mentioned in pg 153 (uncheck Enable master mode).
Now its deviating from the original topic. Please create a new thread for your new Q.I would like to know theoritically what will be difference when working as slave compared to working as master?
To answer that, I have to read the spec in details as to how it behaves. Sorry don't have time for that!Can I say I even don't need to configure access to my program as SPI slave to be controlled from external SPI Master rather just provide access to the register(GPIO pin) to external master?
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