Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

SPEED UP VERILOG SIMULATION WITHOUT SPENDING A PENNY

Status
Not open for further replies.

foster_cn

Member level 4
Joined
Jan 14, 2003
Messages
73
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
442
speed up verilog simulation

good paper
 

foster_cn

Member level 4
Joined
Jan 14, 2003
Messages
73
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
442
speeding up verilog simulations

A recent paper,
suggested a very interesting trick: "Many complex tests require
initializing configuration registers and memories to a known
state. Many times using regular tasks to perform writes and reads to
verify operations can consume 10-50% of total test time. Initializing
registers and memories in bulk can save this time."
 

lipton

Member level 2
Joined
Jul 14, 2002
Messages
46
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
244
Please re-upload
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top