SPECMAN [Verisity E Language]

[ldm]

It seems the E-Language becomes a must-to-have knowlegde in today's ASIC world.

:arrow: Besides cources, what literature would you recommend?

:arrow: Is it possible to reach an evaluation version of the Specman tool of Verisity from somewhere? Is the tool available for a Win2k/XP platform?

:arrow: Any recomendations Where can I download the Specman tool of Verisity? I guess, an evaluation version is good enough for the first time...

 

[eda_wiz]

It seems the E-Language becomes a must-to-have knowlegde in today's ASIC world.

:arrow: Besides cources, what literature would you recommend?

:arrow: Is it possible to reach an evaluation version of the Specman tool of Verisity from somewhere? Is the tool available for a Win2k/XP platform?

:arrow: Any recomendations Where can I download the Specman tool of Verisity? I guess, an evaluation version is good enough for the first time...

verisity has been acquired by cadence. I guess they give evaluation licenses to corporates only..

 

[Johnson]

- Verisity e is not the final answer for verification, you may use others like SystemVerilog, and SystemC.
- It does not have Windows version, just linux and UNIX!
- It is not complete and unified verification env., you have to link it with a logic simulator.
- Another bad news, it does not have eval. version.
- good news: Search the forum for a book which is about e and digital design verification with it.

hope it helps,

 

[ldm]

Does the SystemVerilog has an evaluation version and can be run from under Win2k/WinXP?

 

[jammed]

SystemVerilog is the language, now maybe what you want are evaluation versions of the tools that support SystemVerilog.

Synopsys VCS and Mentor's Questa both support SystemVerilog.
Questa can be run in Windows.

Contact your tool vendors for evaluation versions. I'm sure they would help you out.

 

[ldm]

Thanks to all for considering the issue.

What 's your oppinion about SystemC vs. SystemVerilog? Which one is prefered for verification tasks?

BTW, what about OpenVera from Synopsys? Is it enough popular? Does it have Win2k/WinXp version?

Why Synopsys did start with development of the SystemVerilog while they have OpenVera? What're pros and cons of each tool?

Thanks again for considering this topic.

 

[nagraj]

Thanks to all for considering the issue.

What 's your oppinion about SystemC vs. SystemVerilog? Which one is prefered for verification tasks?

BTW, what about OpenVera from Synopsys? Is it enough popular? Does it have Win2k/WinXp version?

Why Synopsys did start with development of the SystemVerilog while they have OpenVera? What're pros and cons of each tool?

Thanks again for considering this topic.

Hi,

They all used to do verification of designs. SystemC has evolved more of modelling language for design verification.

System Verilog Brings unification of design and verification under one roof. Where as vera,e are purely verification languages.


Thanks

 

[babaship]

here it is

Added after 4 minutes:

sorry here it is

 

[maxsnail]

I think systemverilog will NOT popular in next two years,
for ALL SIMULATOR is not stable!!!!
who will use an unstable tool???
that is a bad thing.
I hear some company back to specman.

 

[megastar007]

Design Veriifciation with E by Samir Palnitkar covers basics of e language

 

[darylz]

Though SV is not fully supported by tools, but main features are already ready in VCS/Modelsim, etc, alongh with the methodoldgies... It's already enough for functional verifications.

 

[nagraj]

I think systemverilog will NOT popular in next two years,
for ALL SIMULATOR is not stable!!!!
who will use an unstable tool???
that is a bad thing.
I hear some company back to specman.

I think this isn't true. System Verilog is now looks to be very stable from Both Mentor and SYNOPSYS. Cadence seems to be fallen a short of time but may come ahead with both e and systemverilog in same tool.