- Verisity e is not the final answer for verification, you may use others like SystemVerilog, and SystemC.
- It does not have Windows version, just linux and UNIX!
- It is not complete and unified verification env., you have to link it with a logic simulator.
- Another bad news, it does not have eval. version.
- good news: Search the forum for a book which is about e and digital design verification with it.
I think systemverilog will NOT popular in next two years,
for ALL SIMULATOR is not stable!!!!
who will use an unstable tool???
that is a bad thing.
I hear some company back to specman.
Though SV is not fully supported by tools, but main features are already ready in VCS/Modelsim, etc, alongh with the methodoldgies... It's already enough for functional verifications.
I think systemverilog will NOT popular in next two years,
for ALL SIMULATOR is not stable!!!!
who will use an unstable tool???
that is a bad thing.
I hear some company back to specman.
I think this isn't true. System Verilog is now looks to be very stable from Both Mentor and SYNOPSYS. Cadence seems to be fallen a short of time but may come ahead with both e and systemverilog in same tool.