Hi,
For the Q1, i believe you are asking whether you can declare data items within a unit. Yes it is possible. Please refer to the following code:
<'
unit try {
addr : int(bits:8 );
keep addr in [1..10];
data : byte;
keep data in [20..40];
enable : bit;
};
extend sys {
t1 :try is instance;
run() is also {
print t1.addr;
print t1.data;
print t1.enable;
gen t1.addr;
print t1.addr;
gen t1.data;
print t1.data;
gen t1.enable;
print t1.enable;
};
};
'>
Upon running this code in specview, the following is the output:
Starting the test ...
Running the test ...
t1.addr = 6
t1.data = 33
t1.enable = 1
t1.addr = 3
t1.data = 40
t1.enable = 0
I am still not clear about the second question. If you mean the instantiation of verification components like units, bfms etc., then yes they can be instantiated. Can you elaborate more on this?