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Specific Verilog questions...

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XoioX

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Hi everyone,

I am going through a piece of code (in Verilog and converting it to VHDL) and although I can simulate it to check what it does, I'd like to make sure I understand the principle behind this line

InputComEncoded = InputCom[3] ? 2'b00 : 2'b10;

Where InputComEncoded and InputCom are defined as:

input [3:0] InputCom;
reg [1:0] InputComEncoded

Am I right to think that InputCom[3] only refers to 1 bit (MSB) of InputCom?

In which case, what is really going on when I compare a 2 bit word with a single bit signal?

When using this conditional statement: A = B ? m : n
Am I right to think that if A = B then A = m else A = n ?

Thanks for your help
(yes I am very new with Verilog! ;-) )
 

std_match

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No, it means A = m if B is true, A = n if B is false.

This construct also exists in the programming language C,
with the same meaning.
 
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FvM

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Why don't you check with a Verilog text book or compiler manual? It's not so effective to guess about the meaning of language contructs.

Am I right to think that if A = B then A = m else A = n ?
So you mean, that A is both receiving the result and used in the compare? Sounds strange, isn't it?
The Verilog c?x:y construct is identical to C language, the c term is tested for equality to zero. It can be replaced by a conditional VHDL assignment

Code:
InputComEncoded <= "00" if InputCom(3)= 1 else "10";
 
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