specifiation to synthesis

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sagar_echip

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pls. suggest any large,well illustrated, design example in verilog,
in networking domain for study purpose.
(from specifiation to synthesis)

thanks
 

There are some good books on EDAboard
 

sagar_echip said:
pls. suggest any large,well illustrated, design example in verilog,
in networking domain for study purpose.
(from specifiation to synthesis)
Click to expand...

If you have interesting in some core such as RISC 51 IP, you can send requisition to DCD Inc.
h**p://www.dcd.com.pl

Good Luck
 

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