chang830
Full Member level 5
cmos ttl interfacing
Hi,
I have a question on the spec defintion on the CMOS(TTL compatible)output.PLs. see the attached pdf file which is the datasheet of the LVDS Quad CMOS differential Line Receiver from National Semiconductor. Pls. see the page 2, the yellow part about the Voh and Vol. I am a bit confused about the Vol definition, the test condition is defined at Iol=2mA, the Vol=0.07V in typ and 0.3V in MAX. We know, in normal, the Iolmax is up to 4mA, so why it is defined at 2mA? I have the concern that it maybe not include the worst case conditions.
Can anyone help to explain it?
Thanks in advance
Hi,
I have a question on the spec defintion on the CMOS(TTL compatible)output.PLs. see the attached pdf file which is the datasheet of the LVDS Quad CMOS differential Line Receiver from National Semiconductor. Pls. see the page 2, the yellow part about the Voh and Vol. I am a bit confused about the Vol definition, the test condition is defined at Iol=2mA, the Vol=0.07V in typ and 0.3V in MAX. We know, in normal, the Iolmax is up to 4mA, so why it is defined at 2mA? I have the concern that it maybe not include the worst case conditions.
Can anyone help to explain it?
Thanks in advance
