Hello Klaus,
the logic analyzer (salaee 16channel) is connected between ground and pin P7
i am using a small board from digilent cmod s6, i have atached the schematic, in the mean time bellow is my constrains file
NET "button" LOC="P9" | IOSTANDARD=LVCMOS33 ; // button 1
NET "uart_out" LOC="P7" | IOSTANDARD=LVCMOS33 ; // board pin4
NET "LD2" LOC="N4" | IOSTANDARD=LVCMOS33 ; // LED2
NET "clk" LOC="N8" | IOSTANDARD=LVCMOS33 ; //
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 125 ns HIGH 50%;
In the schematic, i am ussing button 1 which is connected to pin P9 of the fpga chip, i see it has a permanent pull down resistor so... i am guessing this is not floating at all.
the LED2 which i am using has a ground permanent connection, so from the fpga side a HIGH level is required
what is strange i used a simple code just to see if the button really works.... So in my top module i removed the instance of uart4byte moule, and left only the code bellow just to see whats happening
instead of
output LD2, i used
output reg LD2 so i can assign a value....
always @(posedge clk) begin
if(button == 1) begin
LD2 <=1;
end
else begin
LD2 <=0;
end
so this simple code above is working.... i am beggining to run out of ideeas
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Hello,
i came across this strange solution, its seems index<=0 was causing some trouble..
i kept getting some warning mesages from ISE 14.7
Due to other FF/Latch trimming, FF/Latch <index_1> has a constant value of 0 in block <uart4byte>. This FF/Latch will be trimmed during the optimization process.
Code:
if(index < 7) begin // check to see if we sent all 8 data bits
index <= index +1'd1;//increment by 1
state <= send; // set next state for sending remaining bits
end
else begin // if we sent all the data bits do this...
[COLOR="#FF0000"]index <=0 [/COLOR]; // clear the index counter
state <= stop; // set next state for sending the stop bit
end
end
So i remove that instance of index and moved it bellow in the code, and there is no more warning, and the hardware works !
Code:
if((index+pos)== 31) begin
pos<=8'd0;
state <= idle; // set next state for clearing the data line
end
else begin
state<=start; // back to start
pos <=pos + 8'd8; // increment by 8positions
[COLOR="#008000"] index<=0;[/COLOR]
end
Since i am not a experienced guy in HDL programing, why is this diference since from the logical point of view both should do the same thing?