proacmi2k
Newbie level 2
I need to connect spartan XC3S400(3.3) to Tern 5E micro-controller(5V)
my design has three major components.
1. FPGA(3.3V)
2. External FIFO(3.3V)
4. Tern 5E micro controller(5V)
the FPGA continuoesly generates some data and send it to external FIFO(3.3V).
the FIFO status signals are routed through the FPGA to the 5E micro controller.
the 5E micro controller on the basis of the status signal (Half flag), generates clock cycles to retrieve the data from the FIFO.
the 5E send the READ CLCK through the FPGA to the FIFO.
the 5E general Data Bus and Address bus are being read by the FPGA.
FPGA uses the Address bus of 5E to decode and select particular devices.
the 5E databus is bidirectional to the FPGA. some times 5E put data and some times FPGA put data( the output of FIFO through the FPGA to 5E).
this is the system.
so i need to interface FPGA 3.3 IOz to the 5V IOz of 5E ..
both as inputs and outputs.
i have gone through the all the posts on this issue.
i have come to know that FPGA inputs can be made 5V tolerent so just resistors are required.
but since 3.3V VIH/VOL levels are unappropriate for 5V, so there must be
some translators ICS to connect to FPGA outputs to 5E.
i have come across many solutions,
1. Using MAXIM Translators ICS
2. Using PERICOM VOltage level translators.
so : ) after all this details, my simple question or better, request is that,
kindly from your experience, simple suggest me a IC #, its manufacturer,
(Preferrebly the one available from DIGIKEY), thats much reliable and practially used, or what u suggest.
thanks..
plz also make a direct reply to project_acmi@yahoo.com
my design has three major components.
1. FPGA(3.3V)
2. External FIFO(3.3V)
4. Tern 5E micro controller(5V)
the FPGA continuoesly generates some data and send it to external FIFO(3.3V).
the FIFO status signals are routed through the FPGA to the 5E micro controller.
the 5E micro controller on the basis of the status signal (Half flag), generates clock cycles to retrieve the data from the FIFO.
the 5E send the READ CLCK through the FPGA to the FIFO.
the 5E general Data Bus and Address bus are being read by the FPGA.
FPGA uses the Address bus of 5E to decode and select particular devices.
the 5E databus is bidirectional to the FPGA. some times 5E put data and some times FPGA put data( the output of FIFO through the FPGA to 5E).
this is the system.
so i need to interface FPGA 3.3 IOz to the 5V IOz of 5E ..
both as inputs and outputs.
i have gone through the all the posts on this issue.
i have come to know that FPGA inputs can be made 5V tolerent so just resistors are required.
but since 3.3V VIH/VOL levels are unappropriate for 5V, so there must be
some translators ICS to connect to FPGA outputs to 5E.
i have come across many solutions,
1. Using MAXIM Translators ICS
2. Using PERICOM VOltage level translators.
so : ) after all this details, my simple question or better, request is that,
kindly from your experience, simple suggest me a IC #, its manufacturer,
(Preferrebly the one available from DIGIKEY), thats much reliable and practially used, or what u suggest.
thanks..
plz also make a direct reply to project_acmi@yahoo.com
