Spartan 6 TQG144 package DDR/DDR2 interfacing

[GhostInABox]

I am wondering if there is any restrictions on the FPGA package if we are supposed to design a FPGA + DDR based system. Most of the designs I have seen use FPGA BGA packages when interfacing with DDR/DDR2 chips. Is there any specific constraint that says that We should not design using a FPGA TQG144( Spartan 6 ) package + DDR ?

 

[mrflibble]

I am wondering if there is any restrictions on the FPGA package if we are supposed to design a FPGA + DDR based system. Most of the designs I have seen use FPGA BGA packages when interfacing with DDR/DDR2 chips. Is there any specific constraint that says that We should not design using a FPGA TQG144( Spartan 6 ) package + DDR ?

See UG388, Device Family Support section. The spartan-6's in TQG144 package do not contain any MCB (Memory Controller Block). Seems a reasonably specific constraint to me. ;-)

 

[verylsi]

Hi Ghost,

If you can design a memory controller then there is no constraint.. but it is not recommended if there are some time constraints associated.