Spartan-6 : Clock frequency selection at run-time

[nickagian]

I am doing a project design in Spartan6 that collects data from external ADCs over SPI bus. What I want to do is to be able to select the sampling rate of the ADCs at run-time. Configuration will be done over UART. That actually means that I want to be able to change the clock of the ADCs controller block accordingly at run-time.

Is this possible to be done with a PLL or a DCM? I'm almost 100% that I cannot do this, but just wanted to confirm it from the community. Otherwise, what is the solution that I could use? Create a clock with variable frequency in vhdl, with some counter? Does that create any problem at all?

Thanks!
Nikos

 

[shaiko]

Who is the clock generator for the ADC ?

If you want to change the sampling rate of the ADC - Why do you need to change the frequency of the FPGA itself (because that's what the PLL/DCM is for) ?

 

[nickagian]

I see now that it was somewhat unclear my post. But it is also the fact that I'm quite inexperienced in FPGA design. So normally PLL's and DCM's are used to only provide the main clock of the FPGA, taking as input the frequency of the external oscillator?

In my case, what I have in my mind is not to change the main FPGA clock but only the clock of the ADC controller block, which internally creates the clock for the ADC by using the clock coming into the block. However, changing only the SPI clock generated in the ADC controller is not enough. I need to change the external clock coming in the controller. The reason being that this clock is also used by a memory controller block that takes the ADC results and stores them to a FIFO in order to be written later in the RAM. And I want to have the same clock both for the ADC controller and the memory controller.

 

[shaiko]

If the FPGA is the Clock generator for the ADC then it's very possible (and easy) to change the frequency at runtime.

---------- Post added at 00:26 ---------- Previous post was at 00:22 ----------

I see now that it was somewhat unclear my post. But it is also the fact that I'm quite inexperienced in FPGA design. So normally PLL's and DCM's are used to only provide the main clock of the FPGA, taking as input the frequency of the external oscillator?

Yes.

Does the FPGA generate the clock signal for the ADC ?
I.E - Does the FPGA have an output signal that leads to the ADC's clock pin ?

 

[FvM]

If the design needs to refer to PLL reprogramming at all, which is basically a feature of recent FPGAs like Spartan 6 or similar Altera types, depends on the intended ADC speed range, which hasn't been told. In a moderate speed range, it's probaly easier, to run the design a fixed clock speed and vary the sample trigger frequency only.

In the Xilinx terminology, DCM refers to the subset of available clock processing capabilities that has been available with previous FPGA families. PLL in contrast provides full frequency multiply and divide.

 

[shaiko]

entity clock_generator is
	
	port
	(
		system_clock ,
		reset : in std_logic ;
		
		frequency_limiter : in unsigned ( 15 downto 0 ) ;
		
		generated_clock : buffer 
	) ;	
	   
end entity clock_generator;




architecture synthesizable_clock_generator of clock_generator is

	signal generated_clock_counter : unsigned ( 15 downto 0 ) ; 
	
begin					
	
	process ( reset , system_clock ) is
	begin
		if reset = '1' then
			generated_clock_counter <= ( others => '0' ) ;
			generated_clock <= '0' ;
		elsif rising_edge ( system_clock ) then
			generated_clock_counter <= generated_clock_counter + 1 ;
			if generated_clock_counter = frequency_limiter then
				generated_clock_counter <= ( others => '0' ) ;
				generated_clock <= not generated_clock ; 
			end if ;
		end if ;
	end process ;	
	
end architecture synthesizable_clock_generator;

 

[nickagian]

Does the FPGA generate the clock signal for the ADC ?
I.E - Does the FPGA have an output signal that leads to the ADC's clock pin ?

Yes, exactly. The FPGA provides the conversion clock for the ADC.

If the design needs to refer to PLL reprogramming at all, which is basically a feature of recent FPGAs like Spartan 6 or similar Altera types, depends on the intended ADC speed range, which hasn't been told. In a moderate speed range, it's probaly easier, to run the design a fixed clock speed and vary the sample trigger frequency only.

In the Xilinx terminology, DCM refers to the subset of available clock processing capabilities that has been available with previous FPGA families. PLL in contrast provides full frequency multiply and divide.

And to be more precise, it is a SAR ADC with SPI interface (ADS7863). The conversion clock range is 1-32MHz and the maximum sampling rate is 1MSPS.

If I have understood correctly, your proposal is to keep the clock at the maximum speed and instead change how often I trigger a conversion? Why do you think that would be easier to do?

Anyway, regardless of my application. Can the PLLs really be reprogrammed at run-time? So what simply has to be done is to change the PLL parameters, i.e. the multiply and the divider coefficients? Aren't these parameters in the generic part of the block?

entity clock_generator is
	
	port
	(
		system_clock ,
		reset : in std_logic ;
		
		frequency_limiter : in unsigned ( 15 downto 0 ) ;
		
		generated_clock : buffer 
	) ;	
	   
end entity clock_generator;




architecture synthesizable_clock_generator of clock_generator is

	signal generated_clock_counter : unsigned ( 15 downto 0 ) ; 
	
begin					
	
	process ( reset , system_clock ) is
	begin
		if reset = '1' then
			generated_clock_counter <= ( others => '0' ) ;
			generated_clock <= '0' ;
		elsif rising_edge ( system_clock ) then
			generated_clock_counter <= generated_clock_counter + 1 ;
			if generated_clock_counter = frequency_limiter then
				generated_clock_counter <= ( others => '0' ) ;
				generated_clock <= not generated_clock ; 
			end if ;
		end if ;
	end process ;	
	
end architecture synthesizable_clock_generator;

Thanks for this block, this is what I more or less also had in mind.

 

[FvM]

Yes, I'm suggesting to operate the ADC with constant clock and use variable CONVST pulse frequency. It's easier, because you don't need to go for advanced topics like PLL reprogramming and multiple clock domain designs.

Do you find any hints in the ADC datasheet, that it would be better to reduce the clock frequency at lower conversion speeds, e.g. getting better performance? If so, there's still an option to switch between two or three fixed clock frequencies.

My expectation is, that you need to recalibrate ADC offset and scale when changing the clock.

I'm not using Xilinx FPGAs. From a brief review of Spartan 6 documentation, I got the impression that they support PLL reconfiguration. Of course it's not achieved by changing generics, which have to be set at compile time. Probably, they use additional IP (like Altera does) for reprogramming. But you need to understand the PLL operation details to calculate correct PLL parameters and have to observe various constraints.

So in a short, you won't do it unless absolutely necessary.

 

[nickagian]

Yes, I'm suggesting to operate the ADC with constant clock and use variable CONVST pulse frequency. It's easier, because you don't need to go for advanced topics like PLL reprogramming and multiple clock domain designs.

Do you find any hints in the ADC datasheet, that it would be better to reduce the clock frequency at lower conversion speeds, e.g. getting better performance? If so, there's still an option to switch between two or three fixed clock frequencies.

My expectation is, that you need to recalibrate ADC offset and scale when changing the clock.

To be honest, I have never thought of this possibility. I always had in mind that if I want to run the ADC slower, then the clock is what I should change. However, there is no indication in the datasheet that reducing the clock frequency would be better at lower conversion speeds; not at all. So I guess I can indeed keep the clock at the highest possible frequency and then change the CONVST frequency according to the sampling rate I want. It sounds easier, indeed!

However, there is nothing also mentioned about a need to recalibrate certain parameters of the ADC when changing the clock frequency. But that's ok.

Thanks for the help and this new way (new in reference to what I had in my mind) to operate the ADC with variable sampling rate!

I'm not using Xilinx FPGAs. From a brief review of Spartan 6 documentation, I got the impression that they support PLL reconfiguration. Of course it's not achieved by changing generics, which have to be set at compile time. Probably, they use additional IP (like Altera does) for reprogramming. But you need to understand the PLL operation details to calculate correct PLL parameters and have to observe various constraints.

So in a short, you won't do it unless absolutely necessary.

I see, thank you for this information. I will keep it in mind for future reference.