Hi, if you use Xilinx ISE, you can look at Language templates. The path (from inside ISE sources) is:
Edit->Language Templates, and in case you use VHDL: ->VHDL->Synthesis Constructs->Coding Examples->Misc->Debounce circuit.
The code itself is:
---'begin' keywords**
signal Q1, Q2, Q3 : std_logic;
--**Insert the following after the 'begin' keyword**
process(<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<reset> = '1') then
Q1 <= '0';
Q2 <= '0';
Q3 <= '0';
else
Q1 <= D_IN;
Q2 <= Q1;
Q3 <= Q2;
end if;
end if;
end process;
Q_OUT <= Q1 and Q2 and (not Q3);