SPARTAN 3A FPGA to implement a DDS Controller design

[shitaldesai]

fpga dds

Hi,
I would like to use a SPARTAN 3A FPGA to implement a DDS Controller design. It should be able to configure the DDS for a certain mode of operation which is through a set of programmable registers. I guess a kind of a CPU model should be able to solve the purpose. How do I implement such a design on a FPGA?
Secondly implementing a CPU on a FPGA, what are the techniques to program such a CPU?

Kindly help me with this problem.

Regards
Shital Desai

 

[barry]

dds controller

I started to write a long-winded answer, and then remembered this:
https://www.xilinx.com/support/documentation/ip_documentation/dds.pdf

This is a data sheet for Xilinx's DDS core, but there's plenty of information here for you to design your own.