Spartan 3 FPGA - Design question.

[xOverLoad]

Hello everyone. I would like to excuse myself in the beginning for my bad english.

I got assignment to draw a scheme of circuit in Xilinx on Spartan 3 FPGA board, that would write a word on 4 7-segment display , and it needs to blink every 2 seconds. The word is "radi" which means "IT WORKS".

Well, i wrote binary code for each leather: "R", "A", "D" and "I".

"r" --> "1111010"
"a"--> "0000010"
"d"--> "1000010"
"i"--> "1111011"

I minimized it with bools algebra and made a scheme of that. I have no idea how should i make it blink every 2 seconds, except making 27 bit counter with 27 flip-flops, which would send "1" when it reaches "101111101011110000100000000" which is 100 000 000 Hz, or 100 MHz in decimal= 2 seconds ( using 50 MHz clock on Spartan 3 ofcourse).

The thing is , i dont know if im going in right direction with this "brain-storming" , so im asking you, kind people, not to solve this problem for me , in contrairy just to put me "on the right way" with thinking of solution. Maybe this is the right way it should be done, and ofcourse maybe it isnt, so im open for any suggestions that could help me out to solve my assignment.


Best regards ;-)

 

[barry]

You are on the right track, I think. Are you saying you need to do this project with a schematic rather than VHDL or Verilog? If that is the case, then you ARE going to need a 27-bit counter. The output of this counter would enable the clock input to a flip-flop, so that the output of that flip-flop changes state every two-seconds. You would then use that output to enable your display.

Does that make sense?

Barry

 

[xOverLoad]

You are on the right track, I think. Are you saying you need to do this project with a schematic rather than VHDL or Verilog? If that is the case, then you ARE going to need a 27-bit counter. The output of this counter would enable the clock input to a flip-flop, so that the output of that flip-flop changes state every two-seconds. You would then use that output to enable your display.

Does that make sense?

Barry

Thank you for your reply Barry.

Yep, unfortunately, i have to do this project with a schematic. And yes it does make sense :-D. Ok, well i guess i will make custom simbol for 27-bit counter in Xilinx, and then ill make scheme for 7-segment displays. I'm currently working on this so i will try to update what have i done as soon as possible

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Display has 7 input pins, that means i will have 7 variables for example: letter "r" = "1111010" = "ABCD(not E)F(not G)". And in scheme i have to assign input and output pins. And if i minimize it with Bools algebra and draw a scheme of circuit i will have only 1 output, Y. I understand that , when counter send logic "1" my circuit will respond and it will send those letters on displays , but how can i make it that 1st display shows "r", 2nd one shows "a", 3rd one shows "d", and 4th one shows "i" , how can i assign those pins :S ?

 

[barry]

Is this a display with 4 multiplexed digits? Is there a decoder on the display? If you have four separate 7-segment displays then you will need at least 11 lines to control them.

 

[xOverLoad]

Yesterday i sent e-mail to my mentor, asking him about the assignment. He answered me that i will need this : frequency divider by 1.49 Hz, 2-to-7 decoder and a 2 bit counter which would count 4 states (00,01,10,11), and depending on which state is active that letter will be shown. So, when 00 is active it would turn letter "r" on 1st display, and other 3 displays would be turned off, and when 01 is active, it would turn letter "a", and oter 3 displays would be turned off and so on , and so on. It is possible to do it like that, cause our eye cant see those shifting between letters because of high frequency ( 50 MHz ).

P.S--displays aren't seperated, they are all connected, but you can control only one by putting others in logic "1", cause theyr active on logic "0"

As i mentioned before, sorry for my bad english, i hope you understand me

 

[barry]

Ok, that's what I thought. Your decoder would have four different output states corresponding to the four input states (letters). Not sure what you mean by your 1.49 Hz divider, but I think you understand that the seven segments of the four display s are tied together, and the anode (or cathode, depending on the devices you use) will be enabled one at a time. I don't think you need (or want) to use 50MHz for your enables, 100 Hz would be adequate.

 

[xOverLoad]

Uhm, proffesor told me i will need freq divider, which will divide that 50 MHz 25 times ( with 25 flip-flops, i was thinking i could use flip-flops which are active on rising edge of clock , so when 50Mhz pass through 25 of them , output signal would be 1.49 Hz which is kinda similar to 2 seconds ). Im not sure for that, but i have to check it.

EDIT: my bad, freq divider should be 0.75 Hz which is kinda similar to 2 sec.

 

[xOverLoad]

So far i made 2 bit counter that would count those 4 states, using T flip-flops with activation on falling edge:

**broken link removed**

and frequency divider, which will divide 50MHz clock by 26 times. Which means that on output (CLK_OUT, although i dont know if you can see it on the picture) frequency will be 0.37Hz, which is 1.33 seconds. I could choose between 1.33 sec and 2.7 sec (26 and 27 times). 1.33 sec is more similar to 2 sec than 2.7 sec is.

**broken link removed**

The last thing i need is 2-to-7 demux (decoder), but first i need to do some calculations. So im gonna try to do it in couple of days. I will upload my solution when im done :=)

 

[ads_ee]

why falling edge flops?

Why not use a counter like you originally were thinking of using? That works just as well as a frequency divider and can be run off of the 50 MHz directly leaving you with a single clock domain in the design.

The way you have it now you have flops driving clock inputs, depending on the FPGA architecture this could be a problem. In a 7 series FPGA you'll use an entire slice for each of the 27 stages as the clock input is different for each slice.

 

[xOverLoad]

Im not sure if i understand 2nd paragraph about "slices" xD. Well, anyway, proffessor told me i should do it this way , although he told me it should work with an counter too. I havent done 2-to-7 demux yet, so i dont know if there will be some problems about connecting everything together properly.

Only thing that is bugging me is that how i will assign those 7 output pins of demux, and im not so sure why it should be 7 of them ( maybe cause of 7 leds on 7-segment display, probably is that ). So there are 2 outputs from 2-bit counter,and for first state demux should send 1111010 on those 7 outputs. I have to brain-storm about this one, because im not sure if i get it correctly.

 

[ads_ee]

In the 7 series Xilinx FPGAs a slice has eight flip-flops and four 6-input LUTs. So you would be wasting seven flip flops and possibly three LUTs to implement each register of the clock divider. :-(

Each slice can only accept 1 clock and 1 enable that is shared between all the flip-flops. :-(

I tell you this can be a real problem when you have too many independent clock domains and independent data paths.


Your demux is a 1 to 4 demultiplex with 7-bit data and a 2-bit selector.


hmmm...is your 7-seg dsplay have only 7 inputs and a select or does it have multiple inputs one for each display?
It seems from the previous posts that it's a 7-input with some select lines to select the correct display. If so you really want to have a 7-bit wide 4-to-1 muliplexer (one input for each character)

 

[xOverLoad]

There are 4 7-seg displays on the FPG-a. Although they are all connected (if i want to write a number only on first one, i have to turn off 3 out of 4 displays), there are 4 control lines (1 for each display, AN3, AN2, AN1 and AN0).

 

[ads_ee]

So if there are four 7-seg display interfaces on the FPGA and four control lines then you don't even need a mux at all. I don't see any mention of scrolling the characters so you can directly connect each display to the character it's going to show. You could either use the control lines (assuming they turn on/off the 7-seg display) or if those control lines are load enables of some sort, you would have to mux in either 1111111 or the character (the end result being an OR gate).

 

[xOverLoad]

Yea, i dont need mux, i need demux :-D. Finally ive made it:

**broken link removed**

Now i need to do some K-maping to calculate 4 active displays, and thats it i think. :-D

 

[ads_ee]

Yea, i dont need mux, i need demux :-D. Finally ive made it:

**broken link removed**

Now i need to do some K-maping to calculate 4 active displays, and thats it i think. :-D

So the interface to the four 7-seg displays is over a single 7-bit bus and not 4 x 7-bits (28-bit) interface?

 

[xOverLoad]

Uhm i dont know how to explain. For example, if you want only 1st display to work you have to put 3 others in logic "0" to be off. If you dont, all 4 displays will be on. BUT, there is pin for each display so you can control only 1 if you want to. I dont know if i explained right xD

And ive made a circuit which will control which display will be ON and which ones will be OFF, depending on state in which counter is:
**broken link removed**

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Uhm, they are all connected, but you can choose only one to be ON with input pins of 7-seg displays (AN3,AN2,AN1,AN0)

 

[ads_ee]

I get it. The four 7-seg displays share the same 7-bit output interface from the FPGA, therefore you do have a multiplexer to define which of the four characters are sent over the 7-bit FPGA output bus.

 

[xOverLoad]

I get it. The four 7-seg displays share the same 7-bit output interface from the FPGA, therefore you do have a multiplexer to define which of the four characters are sent over the 7-bit FPGA output bus.

Correct :-D

 

[xOverLoad]

So i finally finished what ive been doing :-D :-D

**broken link removed**

I've added a 3rd input in "aktivnidisleji" and changed from "OR" logic gates to 3-input "AND" gates, so when the frequency divider send logic "1" "aktivnidispleji" will activate and send 4 bits on AN3,AN2,AN1,AN0 outputs, depending on which state counter was in ("brojilo").

Now the last thing i have to do is to check if it works on FPG-a in the university laboratory. But, i tried to simulate the whole thing and it works ! I was so overwhelmed though :lol:

Name of circuits are in croatian language so ill translate them if someone wants to know what is what:
dekoder-decoder (demux)
brojilo-counter (2-bit)
djelitelj_frekvencije- frequency divider
aktivnidispleji-active displays