well I imagine the vrm module 'will' be altering the vcco voltage and the voltage of the internal rails of the fpga.
thats why I ask if its possible to do this.
I have been given contradicting answers to this and i am quite confused...?
I was thinking a watchdog timer could be used to monitor the FPGA activity and when a request for a voltage increase is issued it could communicate to the vrm for the voltage increase.
This is really not an easy question to answer. As long as the voltages are kept in the "legal" working areas of the FPGA, it will be OK, but you can not change the voltages outside of those limitations or the behavior of the device will be unpredictable and eventually mall-function.
its not really strange. its to do with power consumption.
at this voltage level you are talking consumable electronics where ever drop of current counts. ... longer battery life
why send 2.6volts or whatever to a fpga when it might only be performing useful tasks for 60% of the time.
for 30% of the time it could operate on a 'reduced' power saving level.
this is similar to the vrd technique intel uses its processors to communicate to the system bus on switching activity. if the cpu detects a lid closed on a laptop it signals to the system bus using vrd and the voltage is reduced going into the cpu.
my only reservation on this is using fpga seems overly difficult due to the inherently digital nature of it. a mpu like a atmel might be more fesible..? (built in watch dog timer and so forth)
Take a look at it, you may find a lot of interesting options on those FPGAs, specially since some of the devices have Cortex M1 integrated with their FPGAs.