Spacing DRC erro of Metal1

[Fengwei]

Hi.
I am suffering from a lot of DRC errors of Metal1 in P&R of ICC.
Calibre reports a lot of DRC errors while ICC doesn't report any error.
Total number of DRCs = 0
The main errors in Calibre are for Metal 1.
These are adjacent edges, spacing, minarea, spacing of VIA1.
I checked the tf file. The definitions for these parameters are correct.
What is the problem? Can anybody give me some suggestions?

 

[rca]

The technology file must be align with the std cell, and so provided by the std cell provider, is it your case?
Check the via generation rules.

 

[Fengwei]

I got the tech file from the std cell provider. And, the tech file is matched with the design rule. I don't know why ICC can't route correctly.

 

[Fengwei]

After I execute route_zrt_detail, the number of spacing errors is decreased, but the number of Minarea error increases. In the std cell, there is no gds. Some errors can be fixed if the connect to the Metal 1 of std cell. But now, I cannot see anything of std cell. It is also difficult when I use Virtuoso to correct these errors because it may cause a short problem.
Any comments? Please.

 

[Fengwei]

I found the problem. There is no std cell view in CEL folder. It has to be converted by a .lef file. Can anybody tell me a tcl for converting?

 

[loveheihei]

I found the problem. There is no std cell view in CEL folder. It has to be converted by a .lef file. Can anybody tell me a tcl for converting?

FRAM VIEW is enough I think. How many exactly is the DRC errors?