spacing between N+ diffusion and NWELL

[santhua]

hi,

Why should there be a huge spacing between N+ diff and NWELL.
Is there any reason, other than the regions gettting extended during fabrication.

 

[analayout]

Hi,

I think it has some relation with WPE effect


Regards,

Analayout.

 

[santhua]

Hi Analayout ,

Thanx, can you elobrate a little more on it pls

rgds,
santhu

 

[edagops]

could you please explain about the factors
which decides spacing between N+ diffusion and NWELL

 

[k_90]

What technology/process?

do you mean n+diff inside NWELL? ( well tie?)
or
a ntype device?

ESD or NOT ESD?

Please explain your issues so we can help

 

[edagops]

Hi,

What technology/process?

65nm

do you mean n+diff inside NWELL?

diffusion inside NWELL

ESD or NOT ESD?

NOT ESD


Regards,
edagops

 

[santhua]

Let me re-phrase the question,

"The spacing from a nwell to a nmos diffusion region (N+ active outside the nwell)is required only because the regions extend during fabrication process or is there any other reason to it?" .
(And I am not talking about the well tie or N+ diffusion being enclosed by nwell)

Added after 12 minutes:

it is 90nm tech and non esd

 

[k_90]

These rules are set by the fab so if the spacings where too close and overlaped it would create a pnp diode i think.

Being a low geometry it could also be rules to improve Shallow Trench Isolation.

or lastly I could be to help latch-up prevention.

 

[analayout]

Hi ,

There is some explanation about this in the following book.

Art of Analog Layout by Alan Hastings 2nd Edition

p. No . 518

Diffusion near the Channell .

I think you will get some idea from there.

Regards,

Analayout.