Perhaps this relates to your other thread.
Cds always exists. At advanced process nodes you
may see as much Cds from the interconnect as from
the actual intradevice junction and overlap capacitances.
Any derivation will likely be far off unless you know a
lot of detail about junction depths, geometries, side
diffusion and oversizes even if you did have a layout
to look at. Characterize, rather than calculate. Unless
you are good at TCAD and have plenty of time to kill.
Or believe what the models tell you, these hopefully
being data based and reviewed for reasonableness.