source synchronous bus and hold violation

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stanford

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When we send data and clk using source synchronous fashion, and if we assume that skew is ~0, the receiver could have setup and hold violations right?

Why are we more concerned about hold violations with source synchronous bus? Isn't setup violation just as probable as hold violation?
 

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The output data is normally clocked out from the source one clock cycle before it shall be clocked in the destination. This means that there is normally no risk for setup violations if the clock and data signals are routed together. If the data changes too early before the rx clock edge, it is still a hold violation (the data wasn't held long enough).
 

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