source and generated clock in SDC for synthesis

[sun_ray]

Suppose a clock is generated from another clock and hence in the synthesis SDC we provided the create generated clock and also the create clock to create the generated clock and the source clock respectively? Is there any necessity to provide in the synthesis SDC when should setup and hold check will happen for paths that start at source clock domain and ends at generated clock domain?

 

[bright8848]

I don't think it is necessary. The delay though paths is fixed in the same corner no matter clock toggles or not.