Some VCO questions regarding amplitude

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eric0825

Newbie level 6 Some VCO issues

Deal all:
I am a rookie of IC design engineer~I got some problems recently...

1.While design VCO, how to estimate the VCO amplitude? I know it is equal to the bias current multiply by the equivalent tank resistance with a efficiency factor~but here the problem in real design is how to estimate the tank resistance? coz the model provided by foundry of the passive element is not just a resistance in parallel with ideal inductance but more complicated~so how to calculate it or simulate by EDA tool?

2. I've study many papers about VCO, but i can't still understand what differential amplitude and single-end amplitude is, does it means the amplitude reference to another VCO output and reference to ground?

khouly Some VCO issues

with eda tools , u can get the total equivalent resistance of the resonator "tank circuit" ,

or use the EDA directly to get the output power of the VCO "the amplitude"

the differential output is the voltage difference between the two output nodes , most of the VCO's now are fully diferential
about the single ended is the voltage of one of the outputs with reference to the ground

khouly

milkdragon

Member level 3 Re: Some VCO issues

To determine your tank impedance, the simpliest way is to put a ideal AC current source with magnitude of 1, do AC analysis then plot the voltage at that node, which is the impedance also

eric0825

Newbie level 6 Re: Some VCO issues

Thanks for ur help~

Take inductor for example, I usually use the EDA tool to get the S-parameter of the inductor, thus i can get the Y-parameter or Z-parameter, then I calculate the equivalent parallel conductance from the real part of Y-para and equivalent series resistance from real part of Z-para, by the same way, i can also get the equivalent series or parallel inductance from imaginary part of Z-para or Y-para (because of the limited Q-factor, the equivalent series inductance is not equal to parallel ones), i am not sure if this method is correct? Because as i know, the imaginary part of Z-para and Y-para is also contributed by f the parasitic conductance of the inductor, it may result in error of the calculated inductance value.

jecyhale Re: Some VCO issues

eric0825 said:
Deal all:
I am a rookie of IC design engineer~I got some problems recently...

1.While design VCO, how to estimate the VCO amplitude? I know it is equal to the bias current multiply by the equivalent tank resistance with a efficiency factor~but here the problem in real design is how to estimate the tank resistance? coz the model provided by foundry of the passive element is not just a resistance in parallel with ideal inductance but more complicated~so how to calculate it or simulate by EDA tool?

2. I've study many papers about VCO, but i can't still understand what differential amplitude and single-end amplitude is, does it means the amplitude reference to another VCO output and reference to ground?

1. you can calculate. but some time the simulated result is better.
and the phase noise is impacted by the amplitude.

2, differential is the double of singal-end.

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