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# some question on my VCO tuning curve!!!

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#### dillion448

##### Newbie level 2
The VCO i used is popular Maneatis delay cell (symmetric load consist of a diode-connected PMOS device in shunt with an equally sized biased PMOS device). As i know, input voltage is higher, while the out frequency is higher.

but why my tuning curve is not normal? I am confused. why???

plz help me!

doesn't look sensible for it to be bias current, which should

sorry. x(_) is the input voltage, which is used to generate bias voltage VBP and VBN. The input voltage usually is the output of charge pump and LPF in PLL.

Well, I think you should put a cut-line right down the middle
of the "possibilities space" and look at whether you have
linearity in the tuning-voltage-to-set-current chain, and
linearity in the set-current-to-frequency. Break it down.

It's certainly likely that a straight tune voltage to current
conversion could have a deadband, and the curve sure
bears some similarity to a MOSFET I-V gate curve.

Hi
From my understanding we can analyse the curve f vs vin.
We know f(frequency) = 1/2*pi*Rout*Cm
Note: Rout is output impidence looking at either Vout+ or Vout-
Cm is Miller capacitance at Vout+ or Vout-

Rout = 1/gm(pmos)
Cm = (1 + Av)Cgd(nmos) with Av is gain of op amp = gm(nmos)* Rout = gm(nmos)* 1/gm(pmos)

gm(nmos) = W/L*Un*Cox(VGSn - Vtn) = W/L*Un*Cox(Vin+ - Vx - Vtn) Vx is voltage at drain of nmos with Vgate = Vbn

Now we see if Vin+ increase ---> gm(nmos) increase ---> Cm increase ---> frequency decrease

That why your sim is correct

Added after 4 hours 10 minutes:

If you increase Vbn or Vbp the result the same because current bias increase make gm(nmos) of input op amp increase

doibongvui said:
Hi
From my understanding we can analyse the curve f vs vin.
We know f(frequency) = 1/2*pi*Rout*Cm
Note: Rout is output impidence looking at either Vout+ or Vout-
Cm is Miller capacitance at Vout+ or Vout-

Rout = 1/gm(pmos)
Cm = (1 + Av)Cgd(nmos) with Av is gain of op amp = gm(nmos)* Rout = gm(nmos)* 1/gm(pmos)

gm(nmos) = W/L*Un*Cox(VGSn - Vtn) = W/L*Un*Cox(Vin+ - Vx - Vtn) Vx is voltage at drain of nmos with Vgate = Vbn

Now we see if Vin+ increase ---> gm(nmos) increase ---> Cm increase ---> frequency decrease

That why your sim is correct

Added after 4 hours 10 minutes:

If you increase Vbn or Vbp the result the same because current bias increase make gm(nmos) of input op amp increase

if you change the symmetric load as NMOS and use PMOS tail curent bias , you will get the normal positive VCO tuning curve~~

By the way: you Kvco about 1GHz/V, it is so large for Phase noise!

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