some quastions abt P&R .

[vishalkatba]

filler cell lvs

1. how will we decide chip core area ?

2. how to do IR Drop analysis. what kind of infomations does it contain ?

3. what is configuration file ? what does it contains ? for what is it used

4 How to specify Core Utilization factor and Core IO margin? how u will decide this one..

5. what is Block halo?

6. Explain Floor planning ,from scratch to end ?

7. How do u do timing analysis?

8. what is meta file and macro file ?

9. what are constraints you consider for floor planning of Standard Cells?

10. explain In Place Optimization and Timing Delay ?

11. why is Clock Tree Synthesis(CTS) done?

12. Explain LPE

13. why is pre and post-Synthesis and simulation done?

14. what is SITE?

15. how to specify IO constraints ?

16. how to reduce the power /ground Bounce ?

17. which one is best interleaving or non-interleaving for power planning?

18. what is block ring and why is Block ring used?

19. Explain all CT topology? which topology will you prefer for ur design?

20. what CTS Specfications contains?

21. how to do Congestion optimization and balance slew ?

22. Explain Clock Tree By level and By phase delay?

23. why filler cell are uesd?

24. What is Antenna effect and antenna ratio ? how to elimante this ?

25. what is Amoeba placement ? what its use?

26. how to do ILMs for timing optimization?

27. how to do Partitioning the Design?

29. What is AWE(Asymptotic Waveform Estimation) ?

30. why is power planning done and how? which metal should we usefor power and ground ring & strips and why?

31. how do we elimate slack if it occurs during First optimization stage (trial routing)?

32. How do we calculate the die size from cell count of our design?

33. Why Parasitics Extraction for only R and C ,why not L(inductor) ?

34. what are the output files after physical Design?

 

[cafukarfoo]

1. how will we decide chip core area ?
Core area will be decide by the die size, IO pad height and the core to io spacing.
Let say
die area width = 5000um
die area height = 5000um
core to io spacing = 50um
then
core area width = 5000 - (io_pad_height) - (core to io spacing)
core area height = 5000 - (io_pad_height) - (core to io spacing)

2. how to do IR Drop analysis. what kind of infomations does it contain ?
Your need to have routed database for IR drop anaylsis.
You will get some hot spot where the voltage drop is very critical. Normally this hot spot area is far from the power supply of your chip. Due to resistance, the voltage drop along the way from the power supply to the standard cell.

4 How to specify Core Utilization factor and Core IO margin? how u will decide this one..
Core utilization is determine by your project lead. He will determine how congested of your design. Of course, the lower core utilization is easier for implementation wise but the die size will be bigger

5. what is Block halo?
halo is the placement blockage that attached to the macro like RAM. This blockage will move along with the macro if the macro placement change

6. Explain Floor planning ,from scratch to end ?
floorplanning included partitionining, core area shape and location, power planning, partition pin placement, macro placement planning

7. How do u do timing analysis?
You need to completed placement and routing for your design. With the extracted RC from the design, the tool will be able to do timing analysis.

9. what are constraints you consider for floor planning of Standard Cells?
Utilization, power domain, logical connection between the standard cells.

10. explain In Place Optimization and Timing Delay ?
IPO is the placement optimization based on the timing constraint

11. why is Clock Tree Synthesis(CTS) done?
CTS needed to balance the clock tree to avoid unexpected setup and hold violation.

13. why is pre and post-Synthesis and simulation done?
this step is to make sure the functionality of the design doesn't change after synthesis.

14. what is SITE?
SITE is the smallest placement holder to hold the placement of a standard cell

15. how to specify IO constraints ?
You can specify the input delay and output delay for the IO pad.

18. what is block ring and why is Block ring used?
block ring is to power ring attached to a macro.This is to make sure the main power supply can connected to the macro easily

20. what CTS Specfications contains?
CTS spec contain the insertion delay, skew target

21. how to do Congestion optimization and balance slew ?
congestion optimization is done with routing with congestion driven.

23. why filler cell are uesd?
filler cell is used to make sure the power is continous for all the standard cell.

24. What is Antenna effect and antenna ratio ? how to elimante this ?
antena effect mean too many charge will destroy the gate. this can be eliminated by reduce the charge effect or ground the charge.

Antenna ratio = metal area/gate area. This ratio need to be met in order to avoid the gate being destroy by the charge.

25. what is Amoeba placement ? what its use?
amoeba placement is just another placement engine from Cadence. It is called amoeba because of the design appearance after placement

27. how to do Partitioning the Design?
you need to specify the hard boundary for each of your partition. With the help of the EDA tool, you should able to partition the design

30. why is power planning done and how? which metal should we usefor power and ground ring & strips and why?
power planning is done to avoid IR drop issue. To make sure all the cell within the design can get neccesary power supply.

31. how do we elimate slack if it occurs during First optimization stage (trial routing)?
you need to identiy the slack whether it is due to the bad placement or bad timing constraint or bad routing ( route jog )

34. what are the output files after physical Design?
after physical design, the output should be the optimized netlist and the final routed GDS file which you can use for tape out/LVS/DRC verification.