some ports or pins are not connneted ,how to solve it?

[ls000rhb]

unconnected_ports

i compile using DC ,Afert check_design,i find some warining,such as some ports or pins are not connneted to any net,how to solve it?

 

[no_mad]

Hi,

Actually, there are 2 way to remove it.

1. RTL level
- you should remove those unconnected pins and ports at this level.
Optimize your verilog code, make sure that no unused ports and pins tied to VDD and/or VSS in your design.

2. Use DC to remove
- use this command "remove -unconnected_ports"

Hope this helps
-no_mad

 

[ls000rhb]

to :no_mad ,thanks very much!!

 

[amaccormack]

There may be good design reuse reasons for having unconnected ports, so I'd advise against changing the RTL for the sake of a tool that cant remove them. Change your tool if its not up to the job. The command mentioned should help, but Cadence RTL compiler does much more aggressive removal of redundant ports, flip-flops and logic. Sometimes I have thought it has done too much but always in the end it was correct and it actually showed that I needed to fix a bug in the design. Aggressive removal allows faster and smaller designs.

 

[luancao]

In this case, you should look carefully the ports that are not connected. If it is the pins left for scan test i.e test_se, test_si, test_so, the problem will be solved after the scan insertion. In some other case, the pins are left there for extendablity or some other purpose, and you know that, that's also ok for you.

MAKE SURE each unconnected pins are acceptable in your mind. LOOK CAREFULLY, What if you forget to connect the clock on the top of the design when your boss are calling you or you are on the last working day before vacation?

Unconnect pins are cheap but expensive when it is an unwanted one.

 

[eda_ak]

Hello friend:

Unconnected pins are NOT necessarily bad or very harmful at DC level ( I will come back to this statement again).

In other words you may have some pins unconnected but you must know what they are. E.g. you may have spare cells (for ECO) - it is OK or DFT related. Or you may have all Q_bar output pins of D-ff not connected. Actually DC may not even tell about the Q_bar issue.

Going back to 1st sentences. DC may tolerate unconnected pins but Layout tools will not. So if layout tools complains that the Q_bar are un-connected then use this command to fix it:

dc_shell-t> set verilog_show_unconnected_pins true

Hope it helps.

 

[sxqzj]

it's really help to me ,i also encounter this problem!