some logic gates in shift path

[jsathish.challenge]

hi all,
in my design there is some logic is sitting between the Q pin of the flop to SI pin of the flop..is this allowed?.if it is allowed .then how the data shifted is tested in capture mode.?

 

[ic_qiand]

Hi, what do u mean by the "SI pin of the flop" ?

Does it mean signal pin, Data pin of the flop.

 

[jsathish.challenge]

that is path between the Q pin of flop to the SI (shift in ) pin of the flop..

 

[lostinxlation]

Logically, it works as long as SE pin is controlled properly. We have done it for ECO when we needed a mux before a flop, but timing may not be as great since SI pin isn't supposed to be used that way. How shifting works depends on how the design is made, but there are many ways to make it work in test.
For example, you can create a circuit bypassing the logic part from Q of the prev flop to SI pin in shifting mode, and this bypass is controlled by scan enable. You can shift and capture like a normal testing does. Or using D pin for shifting if D is available. Or just skip this flop in shifting if the coverage loss isn't much... Many ways to deal with it.

 

[jpvSoccer]

Hi,

Is the synthesis tool inferring these flops during synthesis and using the SI functionality for mission mode work? or during scan insertion?

I have seen where a scan-flop is misused when the library description does not properly tag it as a scan flop.