Hi iVenky,
q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)
q=d; means a blocking assignment. This will infer a comb structure.
reg is a temporary storage variable which should be used in procedural assignments.
wire is a net used to connect two elements in continuous assignment.
#10...#1....#n are delays to be introduced into the cicuit.
For more details google blocking/non-blocking statemente, using assignment delays in VERILOG and reg type.
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Hi iVenky,
q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)
q=d; means a blocking assignment. This will infer a comb structure.
reg is a temporary storage variable which should be used in procedural assignments.
wire is a net used to connect two elements in continuous assignment.
#10...#1....#n are delays to be introduced into the cicuit.
For more details google blocking/non-blocking statemente, using assignment delays in VERILOG and reg type.