Some doubts in Verilog

[iVenky]

I am new to Verilog (I know VHDL and that's why I am confused)

When is assign used?

sometimes I see

q<= d; and sometimes I see

assign q=d;

Also I can't distinguish "reg" and "wire".

and what is this "#10" and "#1" ?

Thanks in advance. :grin::grin::grin::-D

 

[Baas Rietrot]

q<= d; and sometimes I see

Less than or equal

assign q=d;

Continuous assignment.

Also I can't distinguish "reg" and "wire".

"reg" is a variable, "wire" is a wire/bus.

and what is this "#10" and "#1"

#num, delay num.

 

[sakthikumaran87]

Hi iVenky,

q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)
q=d; means a blocking assignment. This will infer a comb structure.
reg is a temporary storage variable which should be used in procedural assignments.
wire is a net used to connect two elements in continuous assignment.
#10...#1....#n are delays to be introduced into the cicuit.

For more details google blocking/non-blocking statemente, using assignment delays in VERILOG and reg type.

- - - Updated - - -

Hi iVenky,

q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)
q=d; means a blocking assignment. This will infer a comb structure.
reg is a temporary storage variable which should be used in procedural assignments.
wire is a net used to connect two elements in continuous assignment.
#10...#1....#n are delays to be introduced into the cicuit.

For more details google blocking/non-blocking statemente, using assignment delays in VERILOG and reg type.

 

[fiberpcs]

q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)
q=d; means a blocking assignment. This will infer a comb structure.
reg is a temporary storage variable which should be used in procedural assignments.
wire is a net used to connect two elements in continuous assignment.
#10...#1....#n are delays to be introduced into the cicuit.

 

[FvM]

@iVenky. It seems like your "experiment" to learn Verilog by simple Q+A has failed, because none of the posts is fully correct.

I suggest a Verilog text book.

 

[kjm]

Above explanation seems correct, however there is a major difference between "REG" and "WIRE".

WIRE needs to be driven continuously in order to get the output. (i.e. some variable has to drive WIRE continuously to some logic value, otherwise it will show high impedance value).

REG does not needs driver continuously. The value of reg will be retain by the variable till its value changes again. If the input value doesn't changes, there is no need for input to supply value continuously to REG.

 

[FvM]

Above explanation seems correct

Examples for incorrect statements in the above posts:

q<= d;
Less than or equal

No, the shown code is clearly an assignment.

q<= d; means a non-blocking assignment. this will infer a sequential element(D-FF)

Wrong in post #3 and #4, a D-FF is only created if the assignment is executed under an edge sensitive event expression, otherwise it's creating combinational logic.

Finally

some variable has to drive WIRE continuously to some logic value, otherwise it will show high impedance value

A high impedance value will be only generated, if you assign 'z' explicitely, otherwise the signal state is undefined, I think.

P.S.: I have to correct me in the last point. Undriven net type defaults to z.