Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fcount is Port ( clk_measure : in STD_LOGIC; clk_10Mref : in STD_LOGIC; ready : out STD_LOGIC; count_out: out std_logic_vector (31 downto 0); reset : in STD_LOGIC); -- active high end fcount; architecture Behavioral of fcount is signal counted: integer range 0 to 100000000 := 0; --100M range signal timer: integer range 0 to 10000000 := 0; --10M range signal finish : std_logic := '0'; begin -- process to determine 1 second and update output process(clk_10Mref, reset) begin if (reset = '0') then if rising_edge(clk_10Mref) then if (timer = 10000000) then finish <= '1'; count_out <= conv_std_logic_vector(counted,32); end if; if (finish = '0') then timer <= timer + 1; end if; end if; else finish <= '0'; timer <= 0; end if; ready <= finish and not reset; end process; -- process to count rising edges process(clk_measure, clk_10Mref, finish, reset) begin if (reset = '0') then if (finish = '0' and rising_edge(clk_measure)) then counted <= counted + 1; end if; else counted <= 0; end if; end process; end Behavioral;
I don´t see what you mean.I am guessing the update speed is dictated on how fast cnt1 is sampling cnt2 ticks ?
Hi,
Time measurement method...
I'm surprised. Because there is bad resolution at high frequencies:
33 333 333 Hz
25 000 000 Hz
20 000 000 Hz
16 666 667 Hz
14 285 714 Hz
12 500 000 Hz
.... no values inbetween
Klaus
reg overflow;
reg [31:0] counter = 0;
reg [31:0] f_cnt =0;
reg [31:0] value = 0;
parameter f_cnt_max = 1000;
reg ready = 0;
initial begin
// Initialize Inputs
f_clock = 0;
clk = 0;
overflow = 0;
// Wait 100 ns for global reset to finish
#100;
end
always #5 clk =~clk; // ref clock ticks at 10ns period
always #10 f_clock = ~f_clock; // measured clock ticks at 20ns period
always @(posedge clk) begin
if(counter == 50) begin // if reached 1us second
counter<=0; // reset the ref_counter
ready<=1'b1; //
overflow <=1'b1;
value<=f_cnt; // store in a buffer
f_cnt<=0;
end
else begin
counter<=counter+1; //increment counter
ready <= 1'b0; // also activate frequency counter
overflow<=1'b0;
value<=0;
end
end
always@(posedge f_clock ) begin
if(ready == 1'b0) begin
if(f_cnt == f_cnt_max) begin
f_cnt<=0;
end
else begin
f_cnt<= f_cnt+1;
end
end
else begin
f_cnt<=0;
end
end
endmodule
Well, I figured you'd be sampling your signal continuously and your FPGA would be pushing out data at regular interval
Hello whack
The FPGA from the counter side point of view is sampling continuously the signal and after each 1 second, it updates the "ticks_register". This should happen independent from the uart comunication.
The uart module will take as a reference a "data ready" signal to be sure its reading the correct content before sending to the PC
I was suggesting that you keep communication in one direction. Instead of having to ask the FPGA to take the measurement, all you have to do is wait some ms and a new measurement will be ready if your FPGA is sampling continuously. Purpose of this suggestion is simplification.The concept is that i send a command to uart where i tell the fpga "measure the frequency please", then the fpga responds "this is the value (raw 32bit value) ".
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