Oct 29, 2019 #1 V Vlsi24 Newbie level 1 Joined Oct 27, 2019 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 6 If you get this kind of error, please check the input "read verilog file". You might have mistakenly put the pre-synthesized netlist and not the gate level netlist generated from design compiler
If you get this kind of error, please check the input "read verilog file". You might have mistakenly put the pre-synthesized netlist and not the gate level netlist generated from design compiler