this is usually a netlist file. along with this, u ll be given lef files for hardmacros(usually memories i suppose) and lib files. using these files, the backend process starts.
For SOCE 4.2 and before, the design must be given in Verilog gate-leve netlist for P&R.
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From SOCE 5.2, it has integrated RTL Compiler(RC) inside.
So you can also give the design in Verilog RTL code for logic synthesis.
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