after importing a design in SoC encounter 4.2 , i get an warning of 2 modules not present in the lef file, i.e JKFFX1 and TBUFIXL modules are not present in the lef file, which is rgt?
It means there is no LEF view for both the modules. Looks like either they are memory or custom blocks whose LEF has not been extracted or read into the tool. you can grep for these modules in both .lib and lef and see if they are missing in the lef file.
Have you read in all the lef files relevant to your design?
Where did your netlist come from? It seems like it was synthesized with libs other than those you are trying to do P&R with. Do you have a RTL for your design? If you do, it's worth trying to resynthesize the gate-level netlist with the libs that you have at your hand.
First you have to establish the said modules are soft blocks or hard blocks. Two ways to check this -
1. check the .lib files. If the timing model of the block exist in the dot lib, then it is a hard block.
2. if a module is a hard block it sits in the RTL code as a black box.
If that s the case you should request lef of the blocks from the library vendor or IP provider (ie, the same folks who gave you the timing model of those blocks).
If the above is not true, then it is a soft block. You will have to resynthesize rtl bacause some where earlier you may have done synthesis incorrectly.
You specify whatever JKFF and the other one from the libraries you have on hand. Then resynthesis your RTL (if you don't have RTL, use synthesis tool to manipulate the cell reference to the ones you have). After synthesis, just forward the normal Encounter procedure.
In PKS there is a command called 'check_library' that crosschecks cells in LEF and .lib for consistency. cells whose LEF view is missing are reported. Not sure about SOC-E, but consult reference manual.
the two modules are standard cells.. so you standard cell library got screwed up.. check you left and lib file that these cells are there... sometimes in lib it may be present and in lef is got missed up... so while synthesis it checks lib and puts the cell may be because of that you get error iwhen using lef file...
The solution is check the lef and if its not there while synthesis using don't use cells as these two cells... that easiest way..to get rid of problem..
Since its standard cell, and since LEF files only really give pin locations, you could always take a different JK cell with the same size and manually hack the pin locations to what they are in the actual GDS.
I've done it myself after receiving incomplete/unmatching versions of the cell libraries.