SMPS's in parallel: "Master Slave" method

[cupoftea]

Hi,
The attached is two 100W SMPS's in parallel. One (the master) regulates the output voltage, and the other (the slave) simply copies the output current of the master.
In the attached, the slave is obviously with a slower feedback loop than the master. Do you agree that this is indeed a requisite of this "master_slave" configuration?

PDF schem and LTspice sim attached

 

[cupoftea]

Here attached is another way to do multiple SMPS in parallel. This is only for when their Vin's are the same. There is a single error amplifier. The control signal voltage is converted to a PWM, then isolated via a digital isolator, then transported to each controller. This method has absolutely no limit to the number of modules that could be paralleled, because of the single error amp and the control voltage isolation.........the problem when using huge numbers of paralleled modules, is that the ground potential is not the same at each SMPS, so this gives problems....but the attached totally solves this problem. (because for this method, it doesnt matter if ground potential is different at each module).
This method also regulates the output voltage to one value, and doesnt need for example, the vout to get decreased as output current increases...unlike another well know "multiple SMPS in parallel" regime.

Do you agree that the attached is the "de facto" method for paralleling huge numbers of SMPS's when their Vin's are the same?

(LTspice and pdf schem attached)

 

[dick_freebird]

I wouldn't assume anything about "de facto". That's
a random sack of "whatever".

In the POL DC-DC designs I did, we elected to make
a scheme similar to the second approach; "dead head"
the control loop and reconfigure the secondaries'
error amps as unity gain followers from primary EAOUT,
the current mode control backend now makes pulse
peak current track and currents just sum, no feedback
per se on the secondaries to meddle with the primary
loop stability.

 

[cupoftea]

Thanks, yes, that sound slike a really good method that you used. Though as you will know well, it doesnt work when each SMPS has a different input voltage.........for that case, i propose the following....

So, More on the theme of paralleling multiple (large numbers) of SMPS if its OK? (now considering when vin is different for each smps)
When there are large numbers of paralleled SMPS, then the ground potentials at each unit are not the same, and most paralleling techniques thereby become impractical. In such cases, only two paralleling techniques actually work realistically well...

1....Active droop method....where SMPS's give reduced vout as there iout rises.....this works great, and is the cheapest and best method, as long as you dont mind that your light load vout will be 10-15% higher than your max load vout.

2....If the vout is to be the same at all power levels, then you have no option other than to have a digital software based paralleling bus. That is, every single SMPS must continuously report its iout to a master controller. The master controller will compare iout's from all the SMPS's, and tweak them all so that they all share the load. It will do this in such a way, such that the vout stays the same no matter what the load level.
So the master micro, will tweak the reference voltages of all SMPS's, until..
(a) they all share current
(b) they give the same vout, regardless of load.
(Obviosuly, the master micro must measure the overall iout so that it knows what current each SMPS should be carrying.)

Would you agree with the above philosophy?

(the attached shows two paralleled SMPS that share well, but it gives an output voltage which changes by +15% at light load. -Demo'ing that method 2 is needed when vout must be the same whatever the loading. LTspice and pdf schem attached)

By the way, i notice a chip called UC3907 puports to be able to handle multiple SMPS in parallel...but it seems way overcomplicated, and method 2 above looks much more cheap and simple, and just as effective. Would you agree?
UC3907:

https://www.ti.com/product/UC3907

 

[dick_freebird]

I don't think that current sharing accuracy matters as
long as

1) No converter exceeds its output current rating
2) voltage is delivered correctly.

The primary controller should be the only one
whose opinion matters - it needs to sense the
reference ground (wherever that may be) and
the critical VOUT (likewise) and control current
in aggregate to "make it so".

I also don't think it matters a lot, if the various
paralleled-output converters have different VIN
if they each have their own output inductor. The
currents will be imbalanced if left alone, but don't
most CMC converters have a VIN term in the
current sense circuit and doesn't a current-stop
as input voltage signal, result in (roughly) the
same current limit at all positions, just different
pulse widths (assuming this is a simple buck)
to get the same peak current per power pulse?

 

[cupoftea]

Thanks very much , indeed you are correct, the pllel SMPS having different Vin doesnt matter when they are current mode.......they just have different duty cycles, and the error voltage can be the same for both (or all) of them.
As the attached demo's

...So this means that the method of post #2 is best when there are huge numbers of paralleled SMPS's.

--- Updated Nov 6, 2021 ---

In fact, the attached, would you agree, appears to be the "genuine best" method for putting huge numbers of SMPS's in parallel (and when they have different vin's)......its the best way because there is no degradation of vout in light load...vout is the same whatever the loading...there is one single error amp...and due to the isolation of the control voltage, it really doesnt matter if ground potential is very different at each smps.

The only problem is the pole in the txfer function due to having to smooth out the pwm'd control voltage.

I suppose this woudl be addressed by increasing the PWM frequency.

I am wondering why this technique isnt commonly seen?

(LTspice and pdf schem attached)

 

[cupoftea]

Would you agree that the UC39002 load share controller is good for a few modules in parallel....but for very large numbers of modules, it wont work well because the ground potential at each module will likely be different?

UC39002 Load share controller

https://www.mouser.lu/datasheet/2/405/sluu166a-125104.pdf

 

[FvM]

for very large numbers of modules, it wont work well because the ground potential at each module will likely be different?

No problem as long as sense inputs of individual SMPS are differential.

 

[cupoftea]

Thanks, even with differential inputs, the shear length of a trace carrying an analog voltage would be too risky because of its potential to pick up noise? I mean yes, with differential inputs you get round the issue of the ground potentials being different......but the sheer length of the signal trace?....even if routed with 'go' and 'return' together, its still going to be an issue?.......and of course, it may well be quite a job identifying 'go' and 'return' in such a case?