Thanks, if not being paralleled, then what generally do you take as being the maximum power dissipatable in say a DPAK FET on a 2 layer FR4 PCB with no heatsink, and with it just having thermal copper surrounding it up to 1cm all round, and the bottom layer copper mirroring this area, with thermal vias interconnecting? (1 oz copper on PCB, 1.6mm thick PCB, No fan).
Consider the PCB in a metal enclosure, but not thermal padded to it, and the external ambient being 30 degC....Internal ambient 50degC.
some fets just don't like being hard paralleled, even with 10 ohm gate R's with a batch change you can get a lot of 100MHz gate and drain ringing and increase RFI and field failure
Thanks, so you mean one batch of FETs would not dipsplay the ringing, but another batch of the same FETs would show the ringing if hard paralleled....thats bad news.......coudl be very expensive in terms of field failures.
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The following article suggets that in sync bucks, paralleling fets is ok…maybe the parallel fet problem occurs in other types of converters and not in sync bucks?
https://www.ti.com/lit/wp/snva595a/snva595a.pdf
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The alternative to paralleling, is heatsinking, which is too expensive for us in this application...so the only other alternative is paralleled converters...which is many more components and needs the current sharing circuitry