Assuming that JP7 and 10 are in the correct positions (pins 1 - 2 closed) I can only think that this must still be a power related issue. As you are using Softconsole to debug these jumpers should not need to be changed. I don't know which variant of the board you are using, the one shown on the web is quite a bit different to mine, but on the latest version these positions are to the right if the i/o connector is at the bottom. Otherwise is still sounds like a USB Power supply issue. The JTAG pins are dedicated function, so you cannot disable the jtag functionality by programming the FPGA and the only part of the device which can be program protected is the flash memory, but that woukld not affect the chain integrity. Another option is to set the VPRSM jumper to external supply (pins 2 - 3). If this is set to internal (which it seems to be by default) and you have not implemeted the VPRSM in your design then there will be no 1.5V to power the FPGA. I can't think of anything else.