slow to fast synchronization

[abhi_k11]

If I have data(multi bit) to be transferred from a slow clock domain to fast clock domain, then what kind of synchronization technique can be applied.

Say if sending clock period is 30 ns and receiving clock period is 5 ns then the data will be sampled for atleast 5 cycles in the receiving domain. Will this not create any problem as in the sending domain it is only for one clock cycle and in the receiving domain it is sampled for more no. of cycles.

How should the synchronization be done?

 

[radix]

What you probably want to use is an asynchronous fifo. It handles the clock-domain crossing for you.

If you're using one of the major FPGA vendors tools they should have one available to you. If not you can do a google search on 'asynchronous fifos'.

Radix

 

[abhi_k11]

Asynchronous fifo can be used for synchronization. Basically i wanted to know any other synchronization technique apart from using fifo.

We have handshake based synchronization in the case of data transfer from fast domain to slow domain. But can the handshake synchronization be used for synchronizing data from slow to fast domain as well?

Also if handshake is used for synchronization from fast to slow clock domain then when does this synchronization fail?

 

[sakshi gupta]

Please update whether it is true or not :
1) fifo's can be used for slow to fast & fast to slow crossing
2) Handshake is used from slow to fast & fast to slow crossing .

regards
Sakshi

 

[permute]

21-02-09 17:09 -- post #3, in case anyone was going to respond the the original topic.
fifos allow for the buffering of data, and can cross clock domains from fast to slow, or slow to fast. The actual read bandwidth should be greater/equal than the actual write bandwidth, otherwise the fifo will grow in size.

 

[sakshi gupta]

Can we use Handshake from fast to slow & slow to fast crossings ?

 

[muni123]

Handshake mechanism is not recommended for the burst type data transfers.