slow to fast clock latching

[njsth]

hello everyone,
i am working on ethernet and FPGAs. the serial data is arriving to CPLD at a baud rate of 115200bps. i need to latch it to a higher clock which FPGA expects..say 10MHz . I do not have an option for flash memory to store. All i have is a CPLD with 256 macrocells.

could anyone help me in achieving this?

 

[FvM]

You are still misunderstanding the problem as in your previous thread https://www.edaboard.com/threads/312237/

There's no problem of clock speed. CCLK is a static clock without a minimum frequency specification. The problem is UART decoding. You'll need at least a state machine detecting start bits and counting data bits. You don't necessarily neda a shift registers, instead you can generate a clock pulse for each data bit.

 

[njsth]

thanks for the follow up FvM!

but the problem given to me is different now. i have written the code for extracting the 8 bits and sending them out with a clock for each bit (using state machine) already.

but now i am required to latch it at some MHz . so i am looking for a way to do it..if possible using shift registers.

i have heard the same was implemented for UART using FIFO.

i would like to do the same but with no special memory.

hope i was able to make myself more clear

 

[FvM]

but now i am required to latch it at some MHz . so i am looking for a way to do it..if possible using shift registers.

No idea what that means. All you have to do is to generate a rising CCLK edge for each UART data bit.

 

[njsth]

You are still misunderstanding the problem as in your previous thread https://www.edaboard.com/threads/312237/

You don't necessarily neda a shift registers

could you quote an example where i will need a shift registers ?

 

[ads-ee]

Clarification questions I think you need to answer.

A) Are you trying to say you have to send the FPGA configuration data at a 10MHz clock frequency?

B) If A is true: Are you saying that you want to burst each byte from the UART at 10MHz? (you can't send all the data at 10MHz since you aren't storing anything)

Assuming that A is true and you want to burst the bytes then one way is to use the UART FSM which you designed to load a shift register bit by bit. After you reach the stop bit then you shift the data out to the FPGA along with a CCLK. After each byte is shifted out at 10MHz you'll pause the CCLK and wait for the next UART byte to load into the shift register.

regards

 

[FvM]

could you quote an example where i will need a shift registers ?

You would use a shift register e.g.
- if you already have an UART block that outputs byte data
- you want to manipuate the data, e.g. change the bit order
- if you need to resend the data at a specific rate, using a master clock etc. But this isn't the case in serial slave mode.