fmaximovic
Junior Member level 2
Hi all,
I coded a very, very simple 8-bit adder in VHDL and its Behavioral Simulation ran fine. Its Timing Simulation though gave a terrible result: more than 100 ns to perform a sum on a Virtex 6 board (Speed Grade 3); at least, that's what I see from ISim (Xilinx's surrogate for Modelsim).
I did absolutely nothing with Timing Constraints, I mean I don't even know where the defaults ones are; I don't know whether this might be the problem. Same thing for pin assignment or else; I just wrote the code (actually inside a very small schematic) and clicked on Implement and then Timing Simulation.
Synthesis is optimized for speed.
Ah, I said "very simple 8-bit adder", and what I meant was
aws_tmp := (L1(7) & L1) + (L2(7) & L2);
RES_CV <= aws_tmp;
inside a rising clock if statement, with L1 and L2 8-bit input and RES_CV 9-bit output ports. It was just a test.
Thank you in advance for your answers.
I coded a very, very simple 8-bit adder in VHDL and its Behavioral Simulation ran fine. Its Timing Simulation though gave a terrible result: more than 100 ns to perform a sum on a Virtex 6 board (Speed Grade 3); at least, that's what I see from ISim (Xilinx's surrogate for Modelsim).
I did absolutely nothing with Timing Constraints, I mean I don't even know where the defaults ones are; I don't know whether this might be the problem. Same thing for pin assignment or else; I just wrote the code (actually inside a very small schematic) and clicked on Implement and then Timing Simulation.
Synthesis is optimized for speed.
Ah, I said "very simple 8-bit adder", and what I meant was
aws_tmp := (L1(7) & L1) + (L2(7) & L2);
RES_CV <= aws_tmp;
inside a rising clock if statement, with L1 and L2 8-bit input and RES_CV 9-bit output ports. It was just a test.
Thank you in advance for your answers.