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Slewrate Modeling of a Verilog-A Fully Differential Opamp

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Vitor Przedzmirski

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Hello guys,

I am very interested in modeling a fully differential opamp with GBW, Gain and SR limitations, to analyze a 2nd-order SDM. I found the following post very helpful in this case:

Besides that, the slew-rate is not implemented, and I tried to do it, but had no changes in simulation values. I tried to slew the output current using the slew() function.

Does anyone have already tried to do this succesfully? Any hints? Should I, for example, slew the current in the GM branch, instead of the output?

Thanks in advance. :thumbsup:

- - - Updated - - -

Should, I thought i could edit the post to include a link, but I dont know if its possible/ how to do it.

So, the link mentioned above is to the following thread:

https://www.edaboard.com/threads/290282/
 

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