Hi Srini,
I am not sure , if you are still struggling with the issue.
Before looking into the timing slack numbers,
make sure you have the right constraints
1) proper clock definitions in correct units( DC standard unit is ns , RC standard unit of period is ps )
2) Clock exceptions
3) Design Exceptions
4) Dont USE cells
5) How are the Datapath modules are mapped in your design?
6) Input / Output constraints
7) Number of Logic Levels between stage to stage ( It shouldn't be unreasonable )
8) Once all the above are thoroughly checked, then you can see the timing paths..
a) Are the timing path violations are due to high fanout nets ?
b) Any specific datapath architecure is eating up the frequency ?
c) How is the histogram of violations ?
9) initialtarget is nother command you can play with , if none of the above points help you!!
Hope this information may help you !!