Thats where CTS play main role(thats Y CTS enginers are paid more also ofcourse)..Skew balance is plays main role here..
Coming to Amol's Question,
Positive skew : clock and data flow in the same direction.
Negative skew : clock and data flow in oppositve direction...
Max frequency :
T +Tskew >= Tclktoq + Tlogic + Tsu , so T>= Tclktoq + Tlogic + Tsu +/- Tskew
Note: 1) If Tskew > 0, it improves performance , but makes thold harder to meet.
2) If Tskew <0 , it degrades the perfomance of ckt, but easy to meet hold time.
Best of luck..
Regards,
Sam