Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

skew and max operating frequency

Status
Not open for further replies.

amolpukale

Newbie level 4
Joined
Aug 6, 2007
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,311
How is skew related to max operating frequency ?
by definition skew is the difference in the clock arrival. So it means with increasing skew there is more time for the data at the capture flop ? In that case it would help setup ?

How to interpret correctly ?
Please let me know.

Thanks ..
 

The problem with high skew is hold time violation .....
 

I understand that it would worsen the hold; but my question is its relation with the max operating frequemcy ...
 

The maximum operating frequency get increased or decreased based on the direction of the skew..
For further details there are many topics on this forum dicussing about setup ,hold ,skew and operating frequency ....search in this forum
 

Positive skew -> Max freq increased
Negative skew -> Max freq decreased
 

Hi,
I am not quite in agreement with megastar007. Although what megastar007 says looks fine, but when I consider say for example 3 FFs connected in series, and a +ive skew between FF1 and FF2, there are chances, that this +ive skew may cause a -ive skew for the pair FF2 and FF3. So while the max freq between FF1 and FF2 will increase, it may decrease between FF2 and FF3. So for the overall circuit, the fmax may not increase.
Kr,
Avi
http://www.vlsiip.com
 

Thats where CTS play main role(thats Y CTS enginers are paid more also ofcourse)..Skew balance is plays main role here..

Coming to Amol's Question,
Positive skew : clock and data flow in the same direction.
Negative skew : clock and data flow in oppositve direction...

Max frequency :
T +Tskew >= Tclktoq + Tlogic + Tsu , so T>= Tclktoq + Tlogic + Tsu +/- Tskew

Note: 1) If Tskew > 0, it improves performance , but makes thold harder to meet.
2) If Tskew <0 , it degrades the perfomance of ckt, but easy to meet hold time.

Best of luck..

Regards,
Sam
 

CTS Engineers are paid more??? well thats a secret isn't it?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top