Skew comes from mismatched source impedance or mismatched loads (pF) or mismatched signal path delay (latency) or mismatched voltage swing around Vth of input logic ( 1.4V for LVTTL, Vcc/2 +/-x% for CMOS, etc) for each polarity of transition.
For Example LVTTL uses asymmetric voltages and source impedance such that Norton equivalent impedance gives symmetrical power margin for immunity and tradeoff with load range for voltage margin. It also makes it compatible with legacy TTL threshold of two diode drops.
Differential outputs and inputs offer best source matching for skew with impedance controlled paths and termination to source.