Skew and insertion delay

[limitless_21]

Hi All,

What does Skew and insertion delay depend upon in a design. ? or what are the parameters on which these 2 depend. ?
How do we come to conclusion of closing our design on a particular skew value and the insertion delay value.

Regards
limitless

 

[kenambo]

Hi

The specification depends on your specification. Practically Everyone needs a skew of Zero.
Skew depends on mismatch of the two or more paths you measured.
Regarding Insertion Delay it is the delay where the Clock source is defined and where you measure the signal.
It depends on the logics and blocks in the way between measured edge and defined edge.

Thanks

 

[limitless_21]

Hi kenambo,

Thanks for the reply.
I wanted to know more details on how to close the timing of the design - which also includes skew and latency.

REgards
Limitless

 

[kenambo]

You can check the Timing Closure pdf on Encounter Documents..

It will help you..

 

[D.A.(Tony)Stewart]

Skew comes from mismatched source impedance or mismatched loads (pF) or mismatched signal path delay (latency) or mismatched voltage swing around Vth of input logic ( 1.4V for LVTTL, Vcc/2 +/-x% for CMOS, etc) for each polarity of transition.

For Example LVTTL uses asymmetric voltages and source impedance such that Norton equivalent impedance gives symmetrical power margin for immunity and tradeoff with load range for voltage margin. It also makes it compatible with legacy TTL threshold of two diode drops.

Differential outputs and inputs offer best source matching for skew with impedance controlled paths and termination to source.

 

[imsaurabh]

Hi,

Let me put this in simple words...


So whatever green an red is there is insertion delay. which is mainly due to latency from source of clock.

Now Skew is due o unbalance clock tree...
The difference between capturing clock latency - launching clock latency = skew
having said that, we remove common point inbetween two flops, (In this diag) ill clock defination point.
And then we calculate delay between 2 flops.
Eg consider all the buffersw have 1 unit delay
So ff1 insertion delay is : 5 unit
ff2 insertion delay is : 7 unit

and skew between them is 2 unit

NOTE: Daigram is taken from
https://vlsi-soc.blogspot.in/2013/04/clock-jargon-important-terms.html